Document
M25PX64
64-Mbit, dual I/O, 4-Kbyte subsector erase, serial flash memory with 75 MHz SPI bus interface
Preliminary Data
Features
■ SPI bus compatible serial www.DataSheet4U.com ■ 75 MHz (maximum) clock ■ ■
interface frequency
2.7 V to 3.6 V single supply voltage Dual input/output instructions resulting in an equivalent clock frequency of 150 MHz: – Dual output fast read instruction – Dual input fast program instruction Whole memory continuously read by sending once a fast read or a dual output fast read instruction and an address 64 Mbit Flash memory – Uniform 4-Kbyte subsectors – Uniform 64-Kbyte sectors Additional 64-byte user-lockable, one-time programmable (OTP) area Erase capability – Subsector (4-Kbyte) granularity – Sector (64-Kbyte) granularity – Bulk erase (64 Mbits) in 35 s (typical with VPP = 9 V) Write protections – Software write protection applicable to every 64-Kbyte sector (volatile lock bit) – Hardware write protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2) Deep power-down mode: 5 µA (typical) Electronic signature – JEDEC standard two-byte signature (7117h) – Unique ID code (UID) with 16 bytes readonly, available upon customer request More than 100 000 write cycles per sector More than 20 years data retention Packages – ECOPACK® (RoHS compliant) VDFPN8 (ME) 8 × 6 mm (MLP8)
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SO16 (MF) 300 mils width
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March 2008
Rev 2
1/66
www.numonyx.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
M25PX64
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2
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Serial data output (DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write protect/enhanced program supply voltage (W/VPP) . . . . . . . . . . . . 10 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 2.4 2.5 2.6 2.7 2.8
3 4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Dual input fast program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Subsector erase, sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . 13 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13 Fast bulk erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Active power, standby power and deep power-down modes . . . . . . . . . . 14 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8.1 4.8.2 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 16
4.9
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 6.2 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/66
M25PX64
Contents
6.3 6.4
Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 BP2, .