Document
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32 bit TX System RISC TX19 Family TMP19A71CYFG/UG TMP19A71FYFG/UG
Rev 2.0(Feb.2007)
TMP19A71
Contents
1. Features.................................................................................................................................. 1-1 2. Pin Assignments and Pin Functions ....................................................................................... 2-1 3. Prosessor Core....................................................................................................................... 3-1 4. Memory Map........................................................................................................................... 4-1 5. Clock / Standby Control .......................................................................................................... 5-1 6. Watchdog www.DataSheet4U.com Timer ..................................................................................................................... 6-1
7. Exceptions/Interrupts .............................................................................................................. 7-1 8. I/O Ports.................................................................................................................................. 8-1 9. Debug Support Unit (DSU) ..................................................................................................... 9-1 10. DMA Controller (DMAC) ....................................................................................................... 10-1 11. 16-Bit Timer/Event Counters (TMRBs) ..................................................................................11-1 12. Serial I/O (SIO) ..................................................................................................................... 12-1 13. Analog-to-Digital Converters (ADCs) .................................................................................... 13-1 14. Motor Control Circuit (PMD: Programmable Motor Driver) ................................................... 14-1 15. Encoder Input Circuit ............................................................................................................ 15-1 16. ROM Correction.................................................................................................................... 16-1 17. Flash Memory ....................................................................................................................... 17-1 18. I/O Register Summary .......................................................................................................... 18-1 19. Electrical Characteristics ...................................................................................................... 19-1 20. Package Dimensions ............................................................................................................ 20-1
TMP19A71
32-Bit RISC Microprocessor TX19 Family
TMP19A71FYFG/FYUG/CYFG/CYUG 1. Features
The TX19A core processor contained in the TMP19A71 is a family of high-performance 32-bit microprocessors that offers the speed of a 32-bit RISC solution with the added advantage of a significantly reduced code size of a 16-bit architecture. The instruction set of the TX19A includes the high-performance MIPS32ISA, and is enhanced by the MIPS16e-TXTM Application-Specific Extensions (ASE) based on the highly code-efficient MIPS16eISA of MIPS Technologies, Inc. and with added instructions by Toshiba.
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The TMP19A71 is built on a TX19A core processor and contains a selection of intelligent peripherals. It is suitable for low-voltage and low-power applications. The TMP19A71 has the following features: (1) TX19A core processor (For details, refer to the TX19A Architecture manual.) 1) Two instruction set architecture (ISA) modes: 16-bit ISA for code density and 32-bit ISA for speed • • • • • • • • • • The 16-bit ISA is object-code compatible with the code-efficient MIPS16eTMASE. The 32-bit ISA is object-code compatible with the high-performance TX39 Family. High performance Single clock cycle execution (except for save, restore, jump/branch instructions) 3-operand computational instructions for high instruction throughput 5-stage pipeline On-chip high-speed memory DSP function: Executes 32-bit multiply-accumulate operations (32-bit x 32-bit + 64-bit = 64-bit) in a single clock cycle. Low power consumption Optimized design using a low-power cell library
060116EBP
2) Combines high performance with low power consumption.
• The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design fo.