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25L8005 Dataheets PDF



Part Number 25L8005
Manufacturers MXIC
Logo MXIC
Description MX25L8005
Datasheet 25L8005 Datasheet25L8005 Datasheet (PDF)

MX25L8005 FEATURES 8M-BIT [x 1] CMOS SERIAL FLASH GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 8,388,608 x 1 bit structure • 256 Equal Sectors with 4K byte each - Any Sector can be erased individually • 16 Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast access time: 8.

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MX25L8005 FEATURES 8M-BIT [x 1] CMOS SERIAL FLASH GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 8,388,608 x 1 bit structure • 256 Equal Sectors with 4K byte each - Any Sector can be erased individually • 16 Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE • High Performance - Fast access time: 86MHz serial clock - Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block) • Low Power Consumption - Low active read current: 12mA(max.) at 86MHz, and 4mA(max.) at 33MHz - Low active programming current: 15mA (max.) - Low active erase current: 15mA (max.) - Low standby current: 10uA (max.) - Deep power-down mode 1uA (typical) • Minimum 100,000 erase/program cycles • 10 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Block Lock protection - The BP0~BP2 status bit defines the size of the area to be software protected against Program and Erase instructions. • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) • Status Register Feature • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte Device ID - RES command, 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte Device ID HARDWARE FEATURES • SCLK Input - Serial clock input • SI Input - Serial Data Input • SO Output - Serial Data Output P/N: PM1237 1 REV. 2.3, JUN. 05, 2009 MX25L8005 • WP# pin - Hardware write protection • HOLD# pin - pause the chip without diselecting the chip • PACKAGE - 8-pin SOP (150mil) - 8-pin SOP (200mil) - 8-pin PDIP (300mil) - 8-land SON/WSON (6x5mm), 8-land SON is not recommended for new design - 8-land USON (4x4mm) - All Pb-free devices are RoHS Compliant GENERAL DESCRIPTION The MX25L8005 is a CMOS 8,388,608 bit serial Flash memory, which is configured as 1,048,576 x 8 internally. The MX25L8005 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. The MX25L8005 provide sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or byte /sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current. The MX25L8005 utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. PIN CONFIGURATIONS 8-PIN SOP (150/200mil) 8-PIN PDIP (300mil) CS# 1 SO 2 WP# 3 GND 4 8 VCC 7 HOLD# CS# 1 SO 2 6 SCLK WP# 3 5 SI GND 4 8 VCC 7 HOLD# 6 SCLK 5 SI * 8-LAND SON/WSON (6x5mm), USON (4x4mm) CS# 1 SO 2 WP# 3 GND 4 8 VCC 7 HOLD# 6 SCLK 5 SI PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the device without deselecting the device WP# Write Protection VCC + 3.3V Power Supply GND Ground Note: 8-land SON is not recommended for new design P/N: PM1237 REV. 2.3, JUN. 05, 2009 2 BLOCK DIAGRAM MX25L8005 SI CS# SCLK X-Decoder Address Generator Memory Array Page Bu er Data Register SRAM Bu er Mode Logic State Machine Y-Decoder HV Generator Sense Ampli er Clock Generator Output Bu er SO P/N: PM1237 REV. 2.3, JUN. 05, 2009 3 MX25L8005 DATA PROTECTION MX25L8005 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. • Valid command length checking: The comm.


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