Document
PRELIMINARY
KM681000C Family
Document Title
128K x8 bit Low Power CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0.0 0.1
History
Initial draft First revision - Seperate read and write at ICC, ICC1 ICC = ICC1 → Read : 15mA, Write : 35mA Finalized - Add 70ns speed bin for commercial product and 85ns speed bin for industrial. Revised - Improved operating current Add typical value. ICC Read : 15mA → 10mA(Remove write current) ICC2 : 90mA → 60mA - Speed bin change Remove 45ns from commercial part Remove 55ns and 100ns from industrial part.
Draft Date
November 22, 1995 April 15, 1996
Remark
Design target Preliminary
www.DataSheet4U.com
1.0
September 5, 1996
Final
2.0
November 5, 1997
Final
The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 2.0 November 1997
PRELIMINARY
KM681000C Family
128K x8 bit Low Power CMOS Static RAM
FEATURES
• Process Technology: TFT • Organization: 128K x8 • Power Supply Voltage: 4.5~5.5V • Low Data Retention Voltage: 2V(Min) • Three state output and TTL Compatible • Package Type: 32-DIP-600, 32-SOP-525, 32-TSOP1-0820F/R
CMOS SRAM
GENERAL DESCRIPTION
The KM681000C families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current.
PRODUCT FAMILY
www.DataSheet4U.com Product Family
Power Dissipation Operating Temperature Vcc Range Speed Standby (ISB1, Max) 50µA 10µA 50µA 15µA 60mA 32-SOP 32-TSOP1-F/R Operating (ICC2, Max) PKG Type
KM681000CL KM681000CL-L KM681000CLI KM681000CLI-L
Commercial(0~70°C) 4.5~5.5V Industrial(-40~85°C)
55/70ns
32-DIP, 32-SOP 32-TSOP1-F/R
70ns
PIN DESCRIPTION
A11 A9 A8 VCC A13 WE A15 CS2 CS2 A15 VCC WE N.C A13 A16 A14 A8 A12 A9 A7 A6 A11 A5 OE A4 A10 CS1 A4 A5 A6 A7 I/O6 A12 I/O5 A14 A16 I/O4 N.C VCC A15 CS2 WE A13 A8 A9 A11 I/O8 I/O7
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26
FUNCTIONAL BLOCK DIAGRAM
OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
Clk gen.
Precharge circuit.
N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26
A4 A5 A6 A7 A8 A12 A13 A14 A15 A16
VCC VSS Memory array 1024 rows 128×8 columns
32-TSOP Type1 - Forward
25 24 23 22 21 20 19 18 17
Row select
32-DIP 32-SOP
25 24 23 22 21 20 19 18 17
32-TSOP Type1 - Reverse
24 25 26 27 28 29 30 31 32
A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS1 A10 OE CS1 CS2
I/O1 I/O8
Data cont
I/O Circuit Column select
Data cont
A0
A1
A2
A3 A9 A10 A1.