Document
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
Document Title
128Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev. No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. Release to Final Data Sheet. 1.1. Delete Preliminary. 2.2. Added Data Retention Characteristics. Add 10ns part. Draft Data Aug. 5. 1998 Mar. 3. 1999 Remark Preliminary Final
www.DataSheet4U.com Rev. 2.0
Mar. 3. 2000
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Revision 2.0 March 2000
PRELIMINARY
KM681002C/CL, KM681002CI/CLI
FEATURES
• Fast Access Time 10,12,15,20ns(Max.) • Low Power Dissipation Standby (TTL) : 30mA(Max.) (CMOS) : 5mA(Max.) 0.5mA(Max.) L-ver. only Operating KM681002C/CL-10 : 80mA(Max.) KM681002C/CL-12 : 75mA(Max.) KM681002C/CL-15 : 73mA(Max.) KM681002C/CL-20 : 70mA(Max.) • Single 5.0V±10% Power Supply • TTL Compatible Inputs and Outputs www.DataSheet4U.com • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • 2V Minimum Data Retention; L-ver. only • Center Power/Ground Pin Configuration • Standard Pin Configuration KM681002C/CLJ : 32-SOJ-400 KM681002C/CLT : 32-TSOP2-400CF
CMOS SRAM
GENERAL DESCRIPTION
The KM681002C is a 1,048,576-bit high-speed Static Random Access Memory organized as 131,072 words by 8 bits. The KM681002C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM681002C is packaged in a 400mil 32-pin plastic SOJ or TSOP2 forward.
128K x 8 Bit High-Speed CMOS Static RAM(5.0V Operating)
ORDERING INFORMATION
KM681002C/CL-10/12/15/20 KM681002CI/CLI-10/12/15/20 Commercial Temp. Industrial Temp.
PIN CONFIGURATION(Top View)
A0
1 2 3 4 5 6 7 8 9
32 A16 31 A15 30 A14 29 A13 28 OE 27 I/O8 26 I/O7
FUNCTIONAL BLOCK DIAGRAM
A1 A2 A3
Clk Gen.
A0 A1 A2 A3 A4 A5 A6 A7 A8
Pre-Charge Circuit
CS I/O1 I/O2 Vcc
SOJ/ TSOP2
25 Vss 24 Vcc 23 I/O6 22 I/O5 21 A12 20 A11 19 A10 18 17 A9 A8
Row Select
Vss
Memory Array 512 Rows 256x8 Columns
I/O3 10 I/O4 11 WE A4 A5 12 13 14 15 16
I/O1~I/O8
Data Cont. CLK Gen.
I/O Circuit Column Select
A6 A7
PIN FUNCTION
A9 A10 A11 A12 A13 A14 A15 A16
Pin Name A0 - A16
Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection
CS WE OE
WE CS OE I/O1 ~ I/O8 VCC VSS N.C
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Revision 2.0 Mar.