R8A66120FFA

R8A66120FFA 4M-bit x 2 MULTIPLE FIELD MEMORY Description RJJ03FXXXREJ03F0161-0170 Rev.1.70 May.16.2008 R8A66120FFA is high-speed field memory with two FIFO (First In First Out) memories of 4M-bit, which uses high-performance silicon gate process technology. Features Total memory Capacity 8Mega-bit High speed operation cycle time 10.0ns(Min.) fmax = 100MHz output access time 6.0ns(Max.) Output hold time 1.0ns(Min.) Supply voltage 3.3 ± 0.3V Variable length delay bit Synchronous write/read operation 3 states output Package PLQP0048KB-A (48P6Q-A) ( 48pins 7x7mm body LQFP ) W-CDMA base station, Digital PPC, Digital TV,VTR and so on. www.DataSheet4U.com Application Mode Descriptions 1K-word = 1024-words 1024K-word 4bit bus I/F DA<3:0> CKA WRESA WEA DB<3:0> CKB WRESB WEB 4 1024K-w X 4-bit FIFO 4 1024K-w X 4-bit FIFO 4 QA<3:0> RRESA REA 4 QB<3:0> RRESB REB The 2 pieces of 1024K-word x 4-bit FIFO can be operated completely independently. 2-system individual input 2-system individual output Pin Configuration (Top view) Outline: PLQP0048KB-A (48P6Q-A) REJ03F0161-0170 Rev.1.70 May.16.2008 page 1 of 14 R8A66120FFA Block Diagram Data input DA<3:0> DB<3:0> INPUT BUFFER www.DataSheet4U.com Clock inputs MODE CONTROL CIRCUIT CKA CKB Mode setting input MODE WRITE CONTROL CIRCUIT READ CONTROL CIRCUIT Write control inputs for A-system WRESA WEA MEMORY ARRAY 256K-word x 16-bit 256K-word x 16-bit Read control inputs for A-system RRESA REA READ ADDRESS COUNTER WRI...