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R8A66161DD/SP
16-BIT LED DRIVER WITH SHIFT REGISTER AND LATCH
REJ03F0262-0100 Rev. 1.00 Jan. 16. 2008
DESCRIPTION
R8A66161 is a LED array driver having a 16-bit serial input and parallel output shift register function with direct coupled reset input and output latch function. This product guarantees the output current of 24mA (Vcc =5V case) which is sufficient for anode common LED drive, capable of following 16-bits continuously at the same time. Parallel output is open drain output. In addition, as this product has been designed in complete CMOS, power consumption can be greatly reduced when compared with conventional BIPOLAR or Bi-CMOS products. Furthermore, pin layout ensures the realization of an easy printed circuit. R8A66161 is the succession product of M66311.
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FEATURES
● Anode common LED drive ● VCC 5V or 3.3V single power supply ● High output current: all parallel outputs QA~ QP IOL=24mA (at VCC =5.0V) IOL=12mA (at VCC =3.3V) simultaneous lighting available ● Low power dissipation: 100uW/package (max) (VCC=5.0V, Ta=25 , quiescent state) ● High noise margin: Schmitt input circuit provides responsiveness to a long line length ● Equipped with direct-coupled reset ● Open drain output: (except serial data output SQP) ● Wide operating temperature range: Ta=-40oC~+85oC ● Pin layout facilitates printed circuit wiring. (This layout facilitates cascade connection and LED connection)
APPLICATION
● LED array drive, The various LED display modules ● PPC, Printer, VCR, Mini-compo, Button-Telephone etc. All of LED display equipment
BLOCK DIAGRAM
LOGIC DIAGRAM
QA
1
PARALLEL DATA OUTPUTS SERIAL DATA OUTPUT
QB
2
QC
24
QD
23
QE
22
QF
21
QG
20
QH
19
QI
18
QJ
17
QK
16
QL
15
QM
14
QN
13
QO
11
QP
12
SQP
10
Vcc
3
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
Q CK D S
S
S
S
S
5
4
OE
A
ENABLE SERIAL INPUT DATA INPUT
DATA signal OE signal
PARALLEL DATA OUTPUTS QA QP
SERIAL DATA OUTPUT SQP
8
7
6
S
9
CKS
R CKL GND
SHIFT DIRECT LATCH CLOCK RESET CLOCK INPUT INPUT INPUT
OUTPUT FORMAT
REJ03F0262-0100 Rev.1.00 Jan.16.2008 page 1 of 7
R8A66161DD/SP
PIN CONFIGURATION ( TOP VIEW )
QA QB VCC SERIAL DATA INPUT ENABLE INPUT LATCH CLOCK INPUT A OE CKL
1 2 3 4 5 6 7 8 9 10 11 12 SQP QO QP A OE CKL R CKS QA QB QC QD QE QF QG QH QI QJ QK QL QM QN 24 23 22 21 20 19 18 17 16 15 14 13
PARALLEL DATA OUTPUTS
QC QD QE QF QG QH QI QJ QK QL QM QN PARALLEL DATA OUTPUTS
DIRECT RESET INPUT R
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SHIFT CLOCK INPUT
CKS GND
SERIAL DATA OUTPUT SQP PARALLEL DATA OUTPUTS QO QP
FUNCTIONAL DESCRIPTION
As R8A66161 uses silicon gate CMOS process. It realizes high-speed and high-output currents sufficient for LED drive while maintaining low power consumption and allowance for high noises. Each bit of a shift register consists of two flip-flop having independent clocks for shifting and latching. As for clock input, shift clock input CKS and latch clock input CKL are independent from each other, shift and latch operations being made when “L” changes to “H”. Serial data input A is the data input of the first-step shift register and the signal of A shifts shifting registers one by one when a pulse is impressed to CKS. When A is “H”, the signal of “L” shifts. When the pulse is impressed to CKL, the contents of the shifting register at that time are stored in a latching register, and they appear in the parallel data outputs from QA ~ QP. Outputs QA ~ QP are open drain outputs. To extend the number of bits, use the serial data output SQP which shows the output of the shifting register of the 16th bit. When reset input R is changed to “L”, QA ~ QP and SQP are reset. In this case, shifting and latching register are set. If “H” is impressed to output enable input OE, QA ~ QP reaches the high impedance state, but SQP does not reach the high impedance state. Furthermore, change in OE does not affect shift operation.
FUNCTION TABLE (Note: 1)
Operation mode Reset Shift t1 Shift Latch
operation
Input R CKS CKL L X X H H H H X X X X X X X A X H X L X X OE X L L L L H QA Z QA L QA Z Z
0
Parallel data output QB QC QD Z Z Z QE Z QF Z QG QH Z Z QI Z QJ Z QK QL QM Z Z Z QN QO Z Z
Serial data output
Remarks
QP SQP Z L
Output Lighting H Output Lights-out L
Latch t2 Shift t1 Latch t2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP qO0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 qA qB qC qD qE qF qG qH qI qJ qK qL qM qN qO0 qO0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QB QC QD QE QF QG QH QI QJ QK QL QM QN QO QP qO0 qA0 qB0 qC0 qD0 qE0 qF0 qG0 qH0 qI 0 qJ 0 qK0 qL 0 qM0 qN0 qO0 qO0
0
Output disable
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
qP
Note1:
: Change from low-level to high-level 0 Q : Output state Q before CKL chang.