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R8A66171SP Dataheets PDF



Part Number R8A66171SP
Manufacturers Renesas Technology
Logo Renesas Technology
Description A2RT
Datasheet R8A66171SP DatasheetR8A66171SP Datasheet (PDF)

R8A66171DD/SP A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) REJ03F0269-0100 Rev. 1.00 Feb.19.2008 DESCRIPTION The R8A66171 is an integrated circuit for asynchronous serial data communications. It is used in combination with an 8-bit microprocessor and is produced using the silicon gate CMOS technology. R8A66171 is the succession product of M66230. FEATURES ● Baud rate generator ● 4-byte FIFO data buffer for transmission and reception www.DataSheet4U.com ● Error detection : CRC-CCITT ● W.

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R8A66171DD/SP A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER) REJ03F0269-0100 Rev. 1.00 Feb.19.2008 DESCRIPTION The R8A66171 is an integrated circuit for asynchronous serial data communications. It is used in combination with an 8-bit microprocessor and is produced using the silicon gate CMOS technology. R8A66171 is the succession product of M66230. FEATURES ● Baud rate generator ● 4-byte FIFO data buffer for transmission and reception www.DataSheet4U.com ● Error detection : CRC-CCITT ● Wakeup function ● Majority-voting system by sampling three points of received data ● Transmission / reception data format ( number of bits ) Start bit 1 Data bit 8 Wakeup bit 1 or nil Parity bit 1 or nil Stop bit 1 or 2 ● Transmission speed 500Kbps (max) ● Access time ta (/RD-D) : 100ns ● High output current IOH=-24mA IOL=24mA TxD, /RTS, P0, P1 pins ● Schmitt triggered input RxD, /CTS, /RESET pins ● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V) ● Wide operating temperature range (Ta=-40~85OC) APPLICATION Data communication control that uses microprocessor PIN CONFIGURATION (TOP VIEW) D0 D1 D2 DATA BUS D3 D4 D5 D6 D7 READ CONTROL INPUT WRITE CONTROL INPUT RD WR 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 V CC TxD RxD CTS RTS P0 P1 INT CS RESET X1 X2 TRANSMISSION DATA OUTPUT RECEPTION DATA INPUT CLEAR-TO-SEND INPUT REQUEST-TO-SEND OUTPUT PORT OUTPUT INTERRUPT OUTPUT CHIP SELECT INPUT RESET INPUT CLOCK INPUT CLOCK OUTPUT COMMAND/DATA C/D CONTROL INPUT GND REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 1 of 22 R8A66171DD/SP FUNCTION The R8A66171 is a UART (Universal Asynchronous Receiver/Transmitter) and is used in the peripheral circuit of a MCU. The R8A66171 receives parallel data, converts into serial format, and then transmits the serial data via the TxD pin. The device also receives data via the RxD pin from external circuits and converts it into parallel format, and sends the parallel data via the data bus. BLOCK DIAGRAM Reset input Command/Data control input www.DataSheet4U.com Read control input Write control input Chip select input RESET C/D RD WR CS D0 D1 D2 D3 15 11 9 10 16 READ/ WRITE CONTRO L CIRCUIT 8 24 VCC GND TXD Transmission data output CTS RTS Clear-to-send input Request-to-send output TRANSMIT DATA BUFFER 4-BYTE FIFO 8 TRANSMIT BUFFER 12 23 TRANSMIT CONTROL, ERROR DETECTION CODE GENERATION(CRC) CIRCUIT 8 COMMAND REGISTER 8 STATUS REGISTER 21 1 2 3 4 5 6 7 8 20 Data bus D4 D5 D6 D7 DATA 8 BUS BUFFER RECEIVE CONTROL, ERROR DETECTION(CRC) CIRCUIT 8 RECEIVE DATA BUFFER 4-BYTE FIFO RECEIVE BUFFER 22 19 18 17 RXD P0 P1 INT Reception data input Port output Interrupt output SAMPLING CLOCK Clock input Clock output X1 X2 14 13 BAUD RATE GENERATOR 1/16 DIVISION CIRCUIT TRANSFER CLOCK REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 2 of 22 R8A66171DD/SP OPERATION The R8A66171 is interfaced to a system bus and provides all functions needed for data communication. 16 A0 4 Decoder Address bus Control bus I/OR I/OW RESET Data bus 8 8 C/D CS D0~D7 RD WR RESET www.DataSheet4U.com R8A66171DD/SP Fig.1 Interface between the R8A66171 and MCU system bus When using the R8A66171, it is necessary to program the initial setting, baud rate, character length, CRC, parity, in accordance with the communication system. Once programmed, the communication system functions are executed continuously. When initial setting of R8A66171 is completed, data communication becomes possible. When the transmitter is transmit-enabled (TXEN) by a command instruction and /CTS is low-level, data transfer starts up. If these conditions are not satisfied, data transmission is not executed. Reception is possible when the receiver is receive-enabled (RXEN) by a command instruction. The MCU is able to read data when the interrupt output, /INT, goes low by packet end (PE) or buffer full (BF). While receiving data, the R8A66171 checks for errors and provides status information. It checks for four types of errors : CRC, parity, overrun and framing errors. When an error occurs, R8A66171 continues operation. The error status is maintained until the error reset, (ER) is modified by a command instruction. The access method of the R8A66171 is shown Table 1. C/D L L H H X X RD L H L H H X WR H L H L H X CS L L L L L H Data bus Data bus Data bus Data bus R8A66171 operation MPU operation Receiving data buffer(FIFO) Read receive data Transmit data buffer(FIFO) Write transmit data Status register Command register Read the status Write the command - Data bus : High impedance Data bus : High impedance Note : X="L" or "H" TABLE 1. Access method of the R8A66171 REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 3 of 22 R8A66171DD/SP PIN DESCRIPTIONS Pin Name I/O Function X1 Clock input Input X2 Clock output Output A crystal is externally connected to these pins for generating an internal clock. An external clock signal can be input to X1 instead of a crystal. Then X2 output opened..


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