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R8A66174SP Dataheets PDF



Part Number R8A66174SP
Manufacturers Renesas Technology
Logo Renesas Technology
Description PARALLEL-IN SERIAL-OUT DATA BUFFER
Datasheet R8A66174SP DatasheetR8A66174SP Datasheet (PDF)

R8A66174SP PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO REJ03F0278-0101 Rev. 1.01 Oct.06.2008 DESCRIPTION The R8A66174 is a CMOS LSI with 63-byte FIFO (First-In First-Out Memory). The commands or up to 63bytes data can be stored from 8-bit data bus. The data stored in FIFO can be outputted as serial data by executing command, and when the stored data is outputted all, R8A66174 will output an interrupt request signal. R8A66174 has 2-bit output pins (/OE, LATCH) which can set/reset outside devic.

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R8A66174SP PARALLEL-IN SERIAL-OUT DATA BUFFER WITH FIFO REJ03F0278-0101 Rev. 1.01 Oct.06.2008 DESCRIPTION The R8A66174 is a CMOS LSI with 63-byte FIFO (First-In First-Out Memory). The commands or up to 63bytes data can be stored from 8-bit data bus. The data stored in FIFO can be outputted as serial data by executing command, and when the stored data is outputted all, R8A66174 will output an interrupt request signal. R8A66174 has 2-bit output pins (/OE, LATCH) which can set/reset outside devices by the command, R8A66174 can be connected to peripheral circuits that have a serial latch structure. R8A66174 is the succession product of M66300. FEATURES ● General-purpose www.DataSheet4U.com 8-bit CPU bus compatible ● Built-in 63-byte FIFO ● High-speed output (10Mbps) ● It’s able to connect to LED array driver such as R8A66160 or R8A66161 directly ● Low-noise, high-output circuit IOL=16mA, IOH=-16mA (IOL=4mA, IOH=-4mA for /INT) ● Schmitt input (/RESET) ● Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V) o ● Wide operating temperature range (Ta=-40~85 C) APPLICATION General digital equipment for industrial and home use, panel display controllers, and eraser unit controller for copying machine. PIN CONFIGURATION (TOP VIEW) WRITE INPUT WR D0 D1 D2 D3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Vcc C/D CS RESET INT OE LATCH SDATA SCLK Φ COMMAND/DATA INPUT CHIP SELECT INPUT RESET INPUT INTERRUPT REQUEST OUTPUT OUTPUT ENABLE OUTPUT LATCH OUTPUT SHIFT DATA OUTPUT SHIFT CLOCK OUTPUT CLOCK INPUT DATA BUS D4 D5 D6 D7 GND REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 1 of 11 R8A66174SP BLOCK DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 WR CK 8 SELECTOR 13 SDATA DATA BUS 63 X 8-BIT SRAM SHIFT DATA OUTPUT LOAD 8-BIT SHIFT REGISTER DECODER SELECTOR S COMMAND/ DATA INPUT CHIP SELECT INPUT WRITE INPUT C/D 19 CS 18 WR 1 CK INPUT CONTROL CIRCUIT MATCHING DETECTION CIRCUIT WRITE COUNTER READ COUNTER RD RD CK CK www.DataSheet4U.com COMMAND REGISTER BIT/BYTE CONVERTER F/F GATE 12 CLOCK INPUT INTERRUPT REQUEST OUTPUT RESET INPUT Φ 11 INT 16 DIVIDER SCLK SHIFT CLOCK OUTPUT 14 RESET 17 15 OE LATCH LATCH OUTPUT OUTPUT ENABLE OUTPUT FUNCTIONAL DESCRIPTION The information on data bus D0~D7 is loaded as command when C//D=1, and as data when C//D=0. There are four kinds of commands. (1) Command 1. Five kinds of division ratios of the clock input are set up. (2) Command 2. R8A66174 is set as write mode. The CPU is capable of writing 8-bit parallel data of up to 63 bytes into the internal memory (FIFO) of the R8A66174. (3) Command 3. R8A66174 is set as serial output mode. All data written in the internal memory (FIFO) is outputted as serial data in sync with the shift clock which is set by command 1. Then, each data is outputted from LSB. When all stored data has outputted, R8A66174 will output the interrupt request /INT to CPU. (4) Command 4. cancels the /INT and sets/resets the two control ports (LATCH, /OE). After command4, if command3 is executed immediately, the data which is already written will be re-outputted. FUNCTION TABLE Command Input Control inputs /R 0 1 1 /CS C//D /WR D7 × 1 0 × × 1 × × × × 1 1 1 1 1 1 0 1 *5 *5 0 × × 1 × × 0 × 0 × × 0 D6 × × 0 0 0 0 1 × × × × × × D5 × × 0 0 1 1 0 × × × × × × Data inputs D4 × × 0 1 0 1 0 × × × × × × 0 × 0 × × 1 × × × × × D2 × × × × × D1 0 × 1 × × × D3 × × × D2 × × × D1 × × × D0 × × × 0 *1 0 0 0 0 0 0 0 *3 *3 0 0 0 *1 0 0 0 0 0 0 0 *4 *4 0 0 Outputs SCLK SDATA /INT /OE LATCH Remark Initialize Φ 1/2 division of Φ 1/4 division of Φ 1/8 division of Φ 1/16 division of Φ WRITE MODE setting WRITE operation SERIAL OUT MODE setting - - 1 *1 1 1 1 1 1 1 1 1 1 0 1 1 *2 0 * 2 Memory contents not changed Valid when D7 is high-level 1 2 WRITE MODE 3 SERIAL OUT SERIAL OUT end D2 SERI. OUT MODE 4 D1 set/reset the /OE and LATCH, cancel /INT Note1 *1 : The same operation as *3 and *4 in the SERIAL OUT mode. The output is not changed in other modes. *2 : The output is not changed. *3 : The Φ division pulse which is set by command 1 is outputted on /WR rise. *4 : SDATA (n) is output on SCLK fall (n-1). *5 : Indicates 1 when /WR is 0, don't care when /WR is 1. X : Don't care REJ03F0278-0101 Rev.1.01 Oct.06.2008 Page 2 of 11 R8A66174SP BASIC OPERATION Fig. 1 shows the basic operation flowchart. Data inputs D0~D7 are switched among four commands and 8-bit parallel data by the C//D signal. When C//D is 1, the command is stored in sync with the rise of /WR. For initiate to work this IC, at first command 1 should be stored. Command 1 sets the division ratio for clock input Φ as 5 divisions of 1, 1/2, 1/4, 1/8 and 1/16. (The default ratio is 1.) Then command 2 should be stored. When it is stored, 8-bit parallel data is written into the internal memory (FIFO) on the write cycle of the CPU. The maximum capacity of its FIFO is 63 bytes. www.DataSheet4U.com When the write operation has done, command 3 should be stored. For this action, all dat.


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