Gsps ADC. AT84AS008 Datasheet

AT84AS008 Datasheet PDF, Equivalent


Part Number

AT84AS008

Description

10-Bit 2.2 Gsps ADC

Manufacture

E2V

Total Page 30 Pages
PDF Download
Download AT84AS008 Datasheet PDF


AT84AS008 Datasheet
Features
10-bit Resolution ADC
2.2 Gsps Sampling Rate
Seamless Ascending Compatibility with TS83102G0B 10-bit 2 Gsps ADC
500 mVpp Full-scale Analog Input Range
100Differential or 50Single-ended Analog input and Clock Input
100Differential Outputs
ECL/LVDS Output Compatibility
Functions:
– ADC Gain Adjust and Sampling Delay Adjust
– Data Ready Output with Asynchronous Reset
– Out-of-range Output Bit
www.DataShPeoetw4Uer.cComonsumption: 4.2W
Power supplies:
– Analog: -5V, 5V
– Digital: -5V to -2.2V and 1.5V
Radiation Tolerant
Package: CBGA152 Cavity Down Hermetic Package
Evaluation Board AT84AS008GL-EB
Companion Device:
– DMUX 10-bit 1:2/1:4 LVDS 2.2 Gsps AT84CS001
Performances
– 3.3 GHz Full Power Input Bandwidth (-3 dB)
– Gain Flatness: ±0.2 dB (from DC up to 1.5 GHz)
– Low Input VSWR: 1.2 Maximum from DC to 2.5 GHz
– Single Tone Performances (-1 dBFs):
SFDR = -58 dBc; 8.0 ENOB; SNR = 52 dBc at FS = 1.7 Gsps, FIN = 850 MHz
SFDR = -54 dBc; 7.6 ENOB; SNR = 50 dBc at FS = 2.2 Gsps, FIN = 1.1 GHz
SFDR = -54 dBc, 7.4 ENOB; SNR = 48 dBc at FS = 2.2 Gsps, FIN = 2 GHz
– Dual Tone Performances (IMD3), Fs = 1.7 Gps, (-7dBFS tone):
(Fin1 = 995 MHz, Fin2 = 1005 MHz): IMD3 = 64 dBFS
(Fin1 = 1545 MHz, Fin2 = 1555 MHz): IMD3 = 62 dBFS
(Fin1 = 1945 MHz, Fin2 = 1955 MHz): IMD3 = 59 dBFS
– Low Bit Error Rate (10-11) at 2.2 Gsps
Screening
– Temperature Range for Packaged Device:
0°C < Tc; Tj < 90°C (Commercial C Grade)
-20°C < Tc; Tj < 110°C (Industrial V Grade)
Applications
– Broadband Direct RF Down Conversion
– Wide Band Satellite Receivers
– Phased Array Antennas, Radars and ECM
– High-speed Instrumentation and High-speed Acquisition Systems
– High Energy Physics
– Automatic Test Equipment
10-bit 2.2 Gsps
ADC
AT84AS008
5404A–BDC–11/06

AT84AS008 Datasheet
1. Description
www.DataSheet4U.com
The AT84AS008 10-bit 2.2 Gsps ADC allows accurate digitization of high frequency signals
thanks to the 3.3 GHz analog input bandwidth.
The innovative design of the on-chip Track and Hold (T/H) and digitizing core lead to unprece-
dented dynamic performance at a sampling rate of 2.2 GHz (over the full first Nyquist zone). A
7.6 ENOB is achieved at 2.2 Gsps in Nyquist conditions, using gray encoded digital outputs for
optimum SNR performance.
The AT84AS008 features an enhanced spectral purity and very low noise floor, independent on
frequency and temperature. It is particularly well suited for performance enhancement (i.e.
dithering).
The AT84AS008 is fully compatible with TS83102G0B 10-bit 2 Gsps ADC, allowing zero-effort
system improvement by plug-and-play replacement with the new part.
Figure 1-1. Block Diagram
PGEB B/GB
VIN
VINB
50
50
Track &Hold
GA
CLK
CLKB
50
50
SDA
Clock generation
Logic block
OR
ORB
D9
D9B
D0
D0B
DR
DRB
DECB/ DRRB
DIODE
2. Functional Description
The AT84AS008 is a 10-bit 2.2 Gsps ADC. The device includes a front-end Track and Hold
stage (T/H), followed by an analog encoding stage (Analog Quantizer) which outputs analog
residues resulting from analog quantization. Successive banks of latches regenerate the analog
residues into logical levels before entering an error correction circuitry and a resynchronization
stage followed by 100differential output buffers.
The AT84AS008 works in fully differential mode from analog inputs up to digital outputs.
A differential Data Ready output (DR/DRB) is available to indicate when the outputs are valid
and an Asynchronous Data Ready Reset ensures that the first digitized data corresponds to the
first acquisition.
For sampling rates exceeding 2 Gsps, the gray output encoding is recommended for optimum
SNR performance.
2 AT84AS008
5404A–BDC–11/06


Features Datasheet pdf Features 10-bit Resolution ADC 2.2 Gsps Sampling Rate Seamless Ascending Compat ibility with TS83102G0B 10-bit 2 Gsps A DC 500 mVpp Full-scale Analog Input Ran ge 100Ω Differential or 50Ω Single- ended Analog input and Clock Input 100 Differential Outputs ECL/LVDS Output Compatibility Functions: – ADC Gain Adjust and Sampling Delay Adjust – Da ta Ready Output with Asynchronous Reset – Out-of-range Output Bit www.DataSh eet4U.com • Power Consumption: 4.2W Power supplies: – Analog: -5V, 5V – Digital: -5V to -2.2V and 1.5V • Radiation Tolerant • Package: CBGA152 Cavity Down Hermetic Package • Evalu ation Board AT84AS008GL-EB • Companio n Device: – DMUX 10-bit 1:2/1:4 LVDS 2.2 Gsps AT84CS001 • • • • • • • • 10-bit 2.2 Gsps ADC AT84A S008 Performances 3.3 GHz Full Power I nput Bandwidth (-3 dB) Gain Flatness: 0.2 dB (from DC up to 1.5 GHz) Low Inp ut VSWR: 1.2 Maximum from DC to 2.5 GHz Single Tone Performances (-1 dBFs): SFDR = -58 dBc; 8.0 ENOB; SNR = 52 dBc at FS = 1.7 Gsps, FIN = 850 MHz SF.
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