(AS7C33128FT32B / AS7C33128FT36B) 3.3V 128K x 32/36 Flow Through Synchronous SRAM
February 2005
®
AS7C33128FT32B AS7C33128FT36B
3.3V 128K × 32/36 Flow Through Synchronous SRAM
Features
• • • • • • • O...
Description
February 2005
®
AS7C33128FT32B AS7C33128FT36B
3.3V 128K × 32/36 Flow Through Synchronous SRAM
Features
Organization: 131,072 words × 32 or 36 bits Fast clock to data access: 6.5/7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and Global write
Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby Common data inputs and data outputs
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Logic block diagram
LBO CLK ADV ADSC ADSP A[18:0] 19 Q0 Burst logic Q1 19 D Q CE Address register CLK D DQd Q Byte write registers CLK D DQ Q c Byte write registers CLK D DQb Q Byte write registers CLK D BWa CE0 CE1 CE2 DQa Q Byte write registers CLK D Enable CE register CLK Power down D Enable Q delay register CLK 36/32 DQ[a:d] Q 4 CLK CE CLR
17
19
128K × 32/36 Memory array
GWE BWE BWd
36/32
36/32
BWc
BWb
OE Output buffer
Input registers CLK
ZZ
OE
Selection guide
–65 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 7.5 6.5 275 90 30 -75 8.5 7.5 250 85 30 -80 10 8.0 215 75 30 -10 12 10.0 185 75 30 Units ns ns mA mA mA
2/8/05; v.1.2
Alliance Semiconductor
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