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AS7C33128NTD18B Dataheets PDF



Part Number AS7C33128NTD18B
Manufacturers Alliance Semiconductor Corporation
Logo Alliance Semiconductor Corporation
Description 3.3V 128Kx18 Pipelined SRAM
Datasheet AS7C33128NTD18B DatasheetAS7C33128NTD18B Datasheet (PDF)

April 2005 ® AS7C33128NTD18B 3.3V 128K×18 Pipelined SRAM with NTDTM Features • Organization: 131,072 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Byte write enables • Clock enable for operation hold Logic block diagram A[16:0] 17 D • Multip.

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April 2005 ® AS7C33128NTD18B 3.3V 128K×18 Pipelined SRAM with NTDTM Features • Organization: 131,072 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Byte write enables • Clock enable for operation hold Logic block diagram A[16:0] 17 D • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Address register Burst logic Q 17 17 Write delay addr. registers CLK D Q CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD LBO ZZ DQ [a:b] 18 17 Control logic CLK CLK Write Buffer 128K x 18 SRAM Array D Data Q Input Register CLK 18 18 18 18 CLK CEN CLK OE Output Register 18 OE DQ [a:b] Selection Guide -200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3.0 375 135 30 -166 6 166 3.5 350 120 -133 7.5 133 4 325 110 Units ns MHz ns mA mA mA 30 30 4/28/05; v.1.3 Alliance Semiconductor P. 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. AS7C33128NTD18B ® 2 Mb Synchronous SRAM products list1,2 Org 128KX18 64KX32 64KX36 128KX18 64KX32 64KX36 128KX18 www.DataSheet4U.com 64KX32 64KX36 128KX18 64KX32 64KX36 128KX18 64KX32 64KX36 Part Number AS7C33128PFS18B AS7C3364PFS32B AS7C3364PFS36B AS7C33128PFD18B AS7C3364PFD32B AS7C3364PFD36B AS7C33128FT18B AS7C3364FT32B AS7C3364FT36B AS7C33128NTD18B AS7C3364NTD32B AS7C3364NTD36B AS7C33128NTF18B AS7C3364NTF32B AS7C3364NTF36B Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed3 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.0/10 ns 7.5/8.0/10 ns 7.5/8.0/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O 3 Refer corresponding product datasheets for the latest information on Clock Speed and Clock Access Time availability. PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 4/28/05; v.1.3 Alliance Semiconductor P. 2 of 19 AS7C33128NTD18B ® Pin arrangement for TQFP (top view) www.DataSheet4U.com 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD NC NC A A VDDQ VSSQ NC NC DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 NC VDD NC VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQPb NC VSSQ VDDQ NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TQFP 14x20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS NC VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 NC NC VSSQ VDDQ NC NC NC 4/28/05; v.1.3 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A NC Alliance Semiconductor 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P. 3 of 19 AS7C33128NTD18B ® Functional description The AS7C33128NTD18B family is a high performance CMOS 2 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 18 bits and incorporates a LATE LATE Write. This variation of the 2Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced Write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the device on the same clock edge. If a Read command follows this Write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or Read-Modify-Write operations. NTD™ devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one)cycle pipeline (flowthrough) read latency. Write data is applied two cycles after the Write command and address, allowing the Read www.DataSheet4U.com pipeline to clear. With NTD™, Write and Read operations can be used in any order without producing dead bus cycles. Assert R/W low to perform Write cycles. Byte Write enable controls write access to specific.


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