Document
February 2005
®
AS7C33128NTD32B AS7C33128NTD36B
3.3V 128K×32/36 Pipelined SRAM with NTDTM
Features
• Organization: 131,072 words × 32 or 36 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.0/3.5/4.0 ns • Fast OE access time: 3.0/3.5/4.0 ns • Fully synchronous operation • Asynchronous output enable control • Available in 100-pin TQFP package www.DataSheet4U.com • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for reduced power standby
Logic block diagram
A[16:0] 17
D
Burst logic
CE0 CE1 CE2
Address register
Q
17 17
D
17
Q
CLK
Write delay addr. registers
CLK
17
R/W
BWa
BWb
BWc BWd ADV / LD LBO ZZ
Control logic
Write Data Registers
CLK
CLK
128K x 32/36 SRAM Array
DQ [a:d]
32/36
D
Data Q Input Register
CLK
32/36
32/36
32/36
32/36 CLK
CEN CLK OE
Output Register
32/36
OE
DQ [a:d]
Selection Guide
-200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3.0 375 135 30 -166 6 166 3.5 350 120 30 -133 7.5 133 4 325 110 30 Units ns MHz ns mA mA mA
2/8/05; v.1.5
Alliance Semiconductor
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AS7C33128NTD32B AS7C33128NTD36B
®
4 Mb Synchronous SRAM products list1,2
Org 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 www.DataSheet4U.com 128KX32 128KX36 256KX18 128KX32 128KX36 256KX18 128KX32 128KX36 Part Number AS7C33256PFS18B AS7C33128PFS32B AS7C33128PFS36B AS7C33256PFD18B AS7C33128PFD32B AS7C33128PFD36B AS7C33256FT18B AS7C33128FT32B AS7C33128FT36B AS7C33256NTD18B AS7C33128NTD32B AS7C33128NTD36B AS7C33256NTF18B AS7C33128NTF32B AS7C33128NTF36B Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns 6.5/7.5/8.0/10 ns
1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM
1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners.
2/8/05; v.1.5
Alliance Semiconductor
P. 2 of 18
AS7C33128NTD32B AS7C33128NTD36B
®
Pin arrangement for TQFP (top view)
www.DataSheet4U.com
DQPc/NC DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 NC VDD NC VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 DQPd/NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD NC NC A A
TQFP 14x20mm
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS NC VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC
2/8/05; v.1.5
LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A
Note: Pins 1,30,51,80 are NC for x32
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Alliance Semiconductor
P. 3 of 18
AS7C33128NTD32B AS7C33128NTD36B
®
Functional description
The AS7C33128NTD36B family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as 131,072 words × 32 or 36 bits and incorporates a LATE LATE Write. This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations.
www.DataSheet4U.com pipeline
NTD™ devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one) cycle (flowthrough) read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD™, write and read operations can be used in any orde.