AS7C33128NTF36B

April 2005 ® AS7C33128NTF32B AS7C33128NTF36B 3.3V 128K × 32/36 Flowthrough Synchronous SRAM with NTDTM Features Organization: 131,072 words × 32 or 36 bits NTD™architecture for efficient bus operation Fast clock to data access: 7.5/8.0/10.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control Available in 100-pin TQFP package www.DataSheet4U.com Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Logic block diagram A[16:0] 17 D Address register Burst logic Q 17 CLK CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ D Q 17 Write delay addr. registers CLK Control logic CLK Write Buffer CLK 128K x 32/36 SRAM Array DQ[a,b,c,d] 32/36 D Data Q Input Register CLK 32/36 32/36 32/36 32/36 CLK CEN OE Output Buffer 32/36 OE DQ[a,b,c,d] Selection guide -75 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 8.5 7.5 260 110 30 -80 10 8.0 230 100 30 -10 12 10 200 90 30 Units ns ns mA mA mA 4/13/05, v 1.3 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. AS7C33128NTF32B/36B ® 4 Mb Synchronous SRAM products list1,2 Org 256KX18 128KX32 128KX36 256KX18 128KX...