3.3V 128K x 18 pipeline burst synchronous SRAM
February 2005
®
AS7C33128PFD18B
3.3V 128K × 18 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words ...
Description
February 2005
®
AS7C33128PFD18B
3.3V 128K × 18 pipeline burst synchronous SRAM
Features
Organization: 131,072 words × 18 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.0/3.5/4.0 ns Fast OE access time: 3.0/3.5/4.0 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package www.DataSheet4U.com Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs
Logic block diagram
LBO
CLK ADV ADSC ADSP A[16:0] CLK CS CLR
Burst logic 17 15 17
17
Q D CS Address
128K × 18 Memory array
register
CLK
18
GWE BWb BWE BWa CE0 CE1 CE2 D DQb Q
18
CLK D DQa Q CLK D
Byte Write registers Byte Write registers Enable register
Q OE
2
Input registers
CLK
CE CLK ZZ
Output registers
CLK
Power down
D Enable Q
delay register
CLK OE
18 DQ [a,b]
Selection guide
–200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 5 200 3.0 375 130 30 –166 6 166 3.5 350 100 30 –133 7.5 133 4 325 90 30 Units ns MHz ns mA mA mA
1/31/05; v.1.2
Alliance Semiconductor
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AS7C33128PFD18B
®
2 Mb Synchronous SRAM produc...
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