AS7C331FT18A

January 2005 ® AS7C331MFT18A 3.3V 1M x 18 Flow-through synchronous SRAM Features Organization: 1,048,576 words x18 bits Fast clock to data access: 6.8/7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available 100-pin TQFP packages Individual byte write and global write Multiple chip enables for easy expansion 3.3 V core power supply 2.5 V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Common data inputs and data outputs Snooze mode for reduced power-standby www.DataSheet4U.com Logic block diagram LBO CLK ADV ADSC ADSP A[19:0] CLK CS CLR Burst logic 20 18 20 20 Q D CS Address register CLK 1M x 18 Memory array 18 18 GWE BWb BWE BWa CE0 CE1 CE2 D DQb Q CLK D DQa Q Byte Write registers Byte Write registers CLK D 2 OE CE CLK ZZ Enable register Q Output buffers Input registers CLK Power down D Enable Q delay register CLK OE 18 DQ[a,b] Selection guide Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) -68 7.5 6.8 285 90 60 -75 8.5 7.5 275 90 60 -85 10 8.5 250 80 60 -10 12 10 230 80 60 Units ns ns mA mA mA 1/21/05, v 1.4 Alliance Semiconductor 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. AS7C331MFT18A ® 16 Mb Synchronous SRAM products list1,2 Org 1MX18 512KX32 512KX36 1MX18 512KX32 512KX36 1MX18 www.DataSheet4U.com 512KX32 5...