(AS7C33256FT32A / AS7C33256FT36A) 3.3V 256K x 32/36 Flow-through synchronous SRAM
November 2004
®
AS7C33256FT32A AS7C33256FT36A
3.3V 256K × 32/36 Flow-through synchronous SRAM
Features
• • • • • • • O...
Description
November 2004
®
AS7C33256FT32A AS7C33256FT36A
3.3V 256K × 32/36 Flow-through synchronous SRAM
Features
Organization: 262,144 words × 32 or 36 bits Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0/4.0 ns Fully synchronous flow-through operation Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs
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Logic block diagram
LBO CLK ADV ADSC ADSP A[17:0] 18 CLK CE CLR Q0 Burst logic Q1
2 2
D Q CE Address register CLK D DQd Q Byte write registers CLK D DQ Q c Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Q
256K × 32/36 Memory array
18
16
18 32/36 32/36
GWE BWE BWd
BWc
BWb
BWa CE0 CE1 CE2
4
OE Output registers CLK
Input registers CLK
ZZ
Power down
D Enable Q delay register CLK 32/36 DQ[a:d]
OE
Selection guide
Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
-75 8.5 7.5 300 110 30
-85 10 8.5 275 100 30
-10 12 10 250 90 30
Units ns ns mA mA mA
11/30/04, v 1.1
Alliance Semiconductor
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AS7C33256FT32A AS7C33256FT36A
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