AS7C33512NTD18A

November 2004 ® AS7C33512NTD18A 3.3V 512K × 18 Pipelined burst Synchronous SRAM with NTDTM Features Organization: 524,288 words × 18 bits NTD™ architecture for efficient bus operation Fast clock speeds to 166 MHz Fast clock to data access: 3.5/4.0 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation www.DataSheet4U.com Common data inputs and data outputs Asynchronous output enable control Available in100-pin TQFP Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3V core power supply 2.5V or 3.3V I/O operation with separate VDDQ Self-timed WRITE cycles “Interleaved” or “Linear burst” modes Snooze mode for standby operation Logic block diagram A[18:0] 19 D Address register Burst logic CLK Q 19 D CE0 CE1 CE2 R/W BWa BWb ADV/LD LBO ZZ CLK Write delay addr. registers CLK Q 19 Control logic CLK Write Buffer 512K x 18 SRAM Array DQ [a:b] 18 D Data Q Input Register CLK 18 18 18 18 CLK CEN CLK Output OE Register 18 OE DQ[a:b] Selection Guide -166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 11/30/04; v.2.1 –133 7.5 133 4 400 100 30 Units ns MHz ns mA mA mA 1 of 19 6 166 3.5 475 130 30 Alliance Semiconductor Copyright © Alliance Semiconductor. All rights reserved. AS7C33512NTD18A ® 8 Mb Synchronous SRAM products list1,2 Org 512KX18 256KX32 256KX36 512KX18 256KX...