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AS7C33512NTD18A Dataheets PDF



Part Number AS7C33512NTD18A
Manufacturers Alliance Semiconductor Corporation
Logo Alliance Semiconductor Corporation
Description 3.3V 512K x 18 Pipelined burst Synchronous SRAM
Datasheet AS7C33512NTD18A DatasheetAS7C33512NTD18A Datasheet (PDF)

November 2004 ® AS7C33512NTD18A 3.3V 512K × 18 Pipelined burst Synchronous SRAM with NTDTM Features • Organization: 524,288 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation www.DataSheet4U.com • Common data inputs and data outputs • Asynchronous output enable control • Available in100-pin TQFP • Byte write enables • Clock enable for operation hol.

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November 2004 ® AS7C33512NTD18A 3.3V 512K × 18 Pipelined burst Synchronous SRAM with NTDTM Features • Organization: 524,288 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous operation www.DataSheet4U.com • Common data inputs and data outputs • Asynchronous output enable control • Available in100-pin TQFP • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Self-timed WRITE cycles • “Interleaved” or “Linear burst” modes • Snooze mode for standby operation Logic block diagram A[18:0] 19 D Address register Burst logic CLK Q 19 D CE0 CE1 CE2 R/W BWa BWb ADV/LD LBO ZZ CLK Write delay addr. registers CLK Q 19 Control logic CLK Write Buffer 512K x 18 SRAM Array DQ [a:b] 18 D Data Q Input Register CLK 18 18 18 18 CLK CEN CLK Output OE Register 18 OE DQ[a:b] Selection Guide -166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 11/30/04; v.2.1 –133 7.5 133 4 400 100 30 Units ns MHz ns mA mA mA 1 of 19 6 166 3.5 475 130 30 Alliance Semiconductor Copyright © Alliance Semiconductor. All rights reserved. AS7C33512NTD18A ® 8 Mb Synchronous SRAM products list1,2 Org 512KX18 256KX32 256KX36 512KX18 256KX32 256KX36 512KX18 www.DataSheet4U.com 256KX32 256KX36 512KX18 256KX32 256KX36 512KX18 256KX32 256KX36 Part Number AS7C33512PFS18A AS7C33256PFS32A AS7C33256PFS36A AS7C33512PFD18A AS7C33256PFD32A AS7C33256PFD36A AS7C33512FT18A AS7C33256FT32A AS7C33256FT36A AS7C33512NTD18A AS7C33256NTD32A AS7C33256NTD36A AS7C33512NTF18A AS7C33256NTF32A AS7C33256NTF36A Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 166/133 MHz 166/133 MHz 166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 1 Core Power Supply: VDD = 3.3V + 0.165V 2 I/O Supply Voltage: VDDQ = 3.3V + 0.165V for 3.3V I/O VDDQ = 2.5V + 0.125V for 2.5V I/O PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 11/30/04; v.2.1 Alliance Semiconductor 2 of 19 AS7C33512NTD18A ® Pin arrangement for TQFP A A CE0 CE1 NC NC BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A A www.DataSheet4U.com 11/30/04; v.2.1 LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSSQ NC NC DQb0 DQb1 VSSQ VDDQ DQb2 DQb3 NC VDD NC VSS DQb4 DQb5 VDDQ VSSQ DQb6 DQb7 DQpb NC VSSQ VDDQ NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TQFP 14 × 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQpa DQa7 DQa6 VSSQ VDDQ DQa5 DQa4 VSS NC VDD ZZ DQa3 DQa2 VDDQ VSSQ DQa1 DQa0 NC NC VSSQ VDDQ NC NC NC Alliance Semiconductor 3 of 19 AS7C33512NTD18A ® Functional description The AS7C33512NTD18A family is a high performance CMOS 8 Mbit synchronous Static Random Access Memory (SRAM) organized as 524,288 words × 18 bits and incorporates a LATE LATE Write. This variation of the 8Mb sychronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations. NTD™ devices use www.DataSheet4U.com the memory bus more efficiently by introducing a write 'latency' which matches the two cycle pipeline and one cycle flowthrough read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD™, write and read operations can be used in any order without producing dead bus cycles. Assert R/W LOW to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied LOW for full 18 bit writes. Write enable signals, along with the write address, are registered on a rising edge of .


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