AS7C33512NTF18A

November 2004 ® AS7C33512NTF18A 3.3V 512K×18 Flowthrough Synchronous SRAM with NTDTM Features Organization: 524,288 words × 18 bits NTD™ architecture for efficient bus operation Fast clock to data access: 7.5/8.5/10 ns Fast OE access time: 3.5/4.0 ns Fully synchronous operation Flow-through mode Asynchronous output enable control www.DataSheet4U.com Available in 100-pin TQFP Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 3.3 core power supply 2.5V or 3.3V I/O operation with separate VDDQ 30 mW typical standby power Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation Logic Block Diagram A[18:0] 19 D Address register burst logic Q 19 CLK CE0 CE1 CE2 R/W BWa BWb ADV / LD FT LBO ZZ 18 CLK D Q 19 Write delay addr. registers CLK Control logic CLK Write Buffer 512K x 18 SRAM array DQ [a,b] D Data Q input register CLK 18 18 18 18 CLK CEN OE Output buffer 18 OE DQ [a,b] Selection Guide -75 Minimum cycle time Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 8.5 7.5 280 120 30 -85 10 8.5 260 110 30 -10 12 10 220 100 30 Units ns ns mA mA mA 11/8/04, v. 1.1 Alliance Semiconductor P. 1 of 18 Copyright © Alliance Semiconductor. All rights reserved. AS7C33512NTF18A ® 8 Mb Synchronous SRAM products list1,2 Org 512KX18 256KX32 256KX36 512KX18 256KX32 256KX36 512KX18 256KX32 www.DataSheet4U...