AN311 GUIDE Datasheet

AN311 Datasheet, PDF, Equivalent


Part Number

AN311

Description

CP2120 PORTING GUIDE

Manufacture

Silicon Laboratories

Total Page 4 Pages
Datasheet
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AN311
AN311
CP2120 PORTING GUIDE
Relevant Devices
This application note applies to the CP2120.
1. Introduction
The CP2120 SPI to SMBus bridge device can be used as a replacement for the Philips SC18IS60x device by
www.DataSheemt4aUk.cionmg only a few minor hardware and firmware design modifications. All firmware and hardware differences
between the SC18IS60x and CP2120 are outlined in Table 1.
Table 1. Improvement and Modification Summary
SCI18IS60x
Up to 6 general purpose I/O pins
96-byte buffers
No transition byte needed
Up to 3 MHz SPI frequency
4.4 mm package size
CP2120
8 general purpose I/O pins
256-byte buffers
Ability to write a data buffer to up to 255
slave address
Edge Triggered Interrupt Source
Ability to read received byte buffer size
SCL Low for SMBus compatibility
Free Bus Detect for SMBus compatibility
Transition byte between SPI command
write and read phases
Up to 1 MHz SPI frequency
SMBus clock configuration
4 mm package size
Section
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.6
2.1.1
2.1.2
2.1.3
3
2. Firmware
The CP2120 responds to all SC18IS60x commands, including all Internal Register reads, writes, and all Internal
Register reads and writes and all SMBus related commands. The CP2120 offers additional Internal Registers and
commands that enhance performance of designs currently using the SC18IS60x device. However, designers must
make certain modifications, which are discussed in the following sections, to their existing SPI Master interface in
order to communicate with the CP2120.
2.1. Added Features
The CP2120 incorporates a number of features not found in the SC18IS60x. SPI Master firmware can take
advantage of these added features to create a more efficient and reliable system.
Rev. 0.1 9/06
Copyright © 2006 by Silicon Laboratories
AN311

AN311
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2.1.1. 256-Byte Data Buffers
The CP2120 uses 256-byte data buffers to send and receive bytes with SMBus slaves. Calls to the Write Number
of Bytes command can transmit up to 255 bytes in a single transaction, while calls to Read Number of Bytes can
store up to 255 bytes of data into a buffer that can then be read by a Read Buffer command call.
The Write After Write command, which transmits to one slave address and then immediately transmits to a second
slave address, can transmit any amount of data as long as the sum of the two buffers’ sizes does not exceed 255
bytes. The Read After Write command can write 255 bytes and then immediately receive 255 bytes, which can
then be retrieved by the SPI Master during a Read Buffer call.
The Write To Multiple Slaves command can write to any number of slaves any data buffer size, as long as the
number of slaves listed in the command plus the number of bytes stored in the data buffer does not exceed 255.
2.1.2. 8 General Purpose I/O Pins
www.DataSheeTtth4hUee.cIOoCmCP2O1N2F0IGoffaenrsd
8 general purpose input/output
IOCONFIG2 Internal Registers.
port pins that
Writes to the
can be configured to either output or
IOSTATE register update logic levels
input using
of port pins
configured as outputs, while reading the IOSTATE register returns instantaneous port pin states.
Device
CP2120
SPI
Slave
EINT
INT
SPI
Master
EINT Enabled, Configured to be
Low-To-High Transition sensitive:
Level Transition On The EINT Pin
Input to EINT
INT Response
EINT Enabled, Configured to be
High-To-Low Transition sensitive:
Level Transition On The EINT Pin
Input to EINT
INT Response
Figure 1. EINT Functionality
2.1.3. Write to Multiple Slaves Command
A SPI Master can transmit an identical data buffer to multiple slave devices using the Write to Multiple Slaves
Command. Once the command, containing both a data buffer and a buffer of SMBus slave addresses, has been
completely transmitted to the CP2120, the device attempts to transmit to each slave in the slave address buffer. If
time-out timers configured through I2CTO and I2CTO2 are enabled, those timers will be initialized, monitored, and
reset during each individual SMBus transfer. When a SMBus device fails to respond, a configured time-out occurs,
or a transaction completes successfully, the CP2120 attempts to communicate with the next slave listed in the
slave address buffer.
2.1.4. Edge-Triggered Interrupt Source
Figure 1 shows the operation of the EINT Edge-triggered interrupt pin. The EINT digital input pin can be enabled
and configured as an edge-triggered interrupt source by writing to the EDGEINT internal register. The pin can be
configured to lower the INT pin when either a low-to-high or a high-to-low logic transition occurs on the EINT pin.
Reading the EDGEINT internal register after an edge triggered interrupt will raise the INT pin back to logic high.
2.1.5. Received Bytes Register
Bytes received through SMBus calls such as Read Number of Bytes are stored in a data buffer. At any time, the
SPI Master can read the size of this data buffer by reading the RXBUFF register. Reading RXBUFF before calling
Read Buffer can help to ensure that the correct number of bytes gets read from the buffer, without missing any
bytes or reading too many and retrieving invalid data.
2 Rev. 0.1


Features A N 3 11 CP2120 P O R T I N G G U I D E Relevant Devices This application note applies to the CP2120. 1. Introduction making www.DataSheet4U.com The CP2120 SPI to SMBus bridge device can be used as a replacement for the Philips SC18IS 60x device by only a few minor hardware and firmware design modifications. All firmware and hardware differences betw een the SC18IS60x and CP2120 are outlin ed in Table 1. Table 1. Improvement an d Modification Summary SCI18IS60x Up to 6 general purpose I/O pins 96-byte buf fers CP2120 8 general purpose I/O pins 256-byte buffers Ability to write a dat a buffer to up to 255 slave address Edg e Triggered Interrupt Source Ability to read received byte buffer size SCL Low for SMBus compatibility Free Bus Detec t for SMBus compatibility No transition byte needed Up to 3 MHz SPI frequency Transition byte between SPI command wri te and read phases Up to 1 MHz SPI freq uency SMBus clock configuration 4.4 mm package size 4 mm package size Section 2.1.1 2.1.2 2.1.3 2.1.4 .
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