SURGE IMMUNITY. AN315 Datasheet

AN315 IMMUNITY. Datasheet pdf. Equivalent


Silicon Laboratories AN315
AN315
ROBUST ELECTRICAL SURGE IMMUNITY
FOR POE PDS THROUGH INTEGRATED PROTECTION
1. Introduction
The Si3400 and Si3401 Power over Ethernet (PoE) powered device (PD) controllers are designed in an efficient
Silicon on Insulator (SOI) process technology, which enables the integration of a robust surge protection function.
Competitive PoE PD devices require external transient voltage suppressors (TVS), such as an SMAJ58A, to
provide surge protection. However, due to their inherently wider range of clamping voltage specifications, external
TVS-based protectors typically necessitate the use of 100 V processes for the PD controller device. This note
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the
and
detailed considerations regarding the Si3400's proprietary surge protection circuitry that
Si3401 devices to yield robust and standards-compliant electrical surge immunity when
used in Power over Ethernet powered device applications.
2. Traditional PD Surge Protection Considerations
As will be discussed later, surge currents of up to 5 A must be tolerated in PoE applications. The surge protector
most often used with PD controllers is an external SMAJ58A TVS diode (D1 in Figure 1).
To
RJ 45 &
Magnetics
B1
B2
D1
VSS
VPOS
RDET
RCLASS
VNEG
VSS
VCC
802.3af
PD I/F
+
Switching
Regulator
SWO
DET
FB
EROUT
VSS
VSS
M1
Opto
Figure 1. Traditional PoE PD Interface and Switching Regulator
(without High Voltage Device Integration)
For example, a standard SMAJ58A TVS from Diodes Incorporated has a maximum operating voltage of 58 V,
25 °C ratings of between 64.4 and 71.2 V at 1 mA, and a clamping voltage under 93.6 V at 4.3 A.
While it is possible to sort individual devices for tighter clamp voltage ratings, the typical maximum clamping
voltage (including temperature variations) when using this type of protector is close to 100 V. Consequently, most
PoE PD controllers are implemented in processes providing a 100 V breakdown voltage.
Rev. 0.2 10/06
Copyright © 2006 by Silicon Laboratories
AN315


AN315 Datasheet
Recommendation AN315 Datasheet
Part AN315
Description ROBUST ELECTRICAL SURGE IMMUNITY
Feature AN315; AN315 ROBUST ELECTRICAL SURGE IMMUNITY F O R P O E PD S T H R O U G H I N T E G R A T E D P R O T E .
Manufacture Silicon Laboratories
Datasheet
Download AN315 Datasheet




Silicon Laboratories AN315
AN315
3. Detailed Description of Si3400 Protection
Si3400 and Si3401 protection consists of a stack of ten, high-current 6.2 V Zener diodes. These lower-voltage
Zener diodes have a lower temperature and process variation than a higher voltage Zener clamp, such as an
SMAJ58A. Consequently, the range of initial breakdown for the complete stack is much tighter: typically <1 V
variation at room temperature (as compared to 6.8 V for the SMAJ58A) and <4 V variation over –40 to +85 °C. Due
to the incremental resistance of the Zener diode stack, the voltage at 0.5 A current typically increases to 73 V, and
the voltage at 5 A current is less than 79 V for the Si3400's on-chip protector. As a result, the Si3400's maximum
clamping voltage of 79 V is considerably lower than the 90 to 100 V range of a typical SMAJ58A TVS protector.
Because the Zener stack is part of the Si3400's internal circuitry, it becomes straightforward to detect a surge
condition internal to the IC. To provide additional protection against high current and longer-duration transients, the
switcher is shut down, and the hot swap switch is turned on with the current limit disabled when current starts to
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switcher section during
allows steering of some
a
of
transient
the surge
event prevents damage to the
current to the switching rectifier
input filter capacitor, which reduces the current in the Zener stack and allows for very high current spike tolerance
without damage.
4. Surge Test Considerations for the Si3400 and Si3401
There are five basic surge conditions that must be accounted for when evaluating surge protection as detailed
below. The Si3400's performance has been tested in all of these conditions with excellent results.
4.1. Standards-Based Surge Testing
IEEE STD™ 802.3-2005 specifies a 1000 V surge tolerance with a 300 nsec virtual front and 50 µsec half value
(as defined in IEC 60060) with an impedance applied via a 402 Ω resistor to each wire in the wire pair. While the
return path is not specified, a worst case interpretation is that the return pair is grounded so that 2.5 A flows in each
of the wires to the PD, resulting in a 5 A surge to the PD.
The 5 A surge will charge the typical 0.1 µF PD input capacitor to 50 V in 1 µsec. After this time, the Zener diode
clamps, and once the hot swap switch is turned on, some of this surge is steered to the switcher input filter
capacitor as well.
The Si3400's performance has been tested with this worst-case interpretation surge condition. All devices tested
survived the standard 1000 V condition for 10 repetitions with substantial margin.
4.2. ESD
An Si3400 isolated EVB (Revision 1.2) was tested for ESD immunity. The test method reference is IEC 61000-4-2.
A Schaffner model NSG 435 ESD gun was used to generate the ESD pulses.
For this test, the connector shield was tied to the Vneg heat sink/isolated ground plane of the Si3400 ISO EVB, and
the ESD pulses were applied to the shield with the output of the EVB grounded. The ESD discharge path in this
case would be through the 1000 pF high-voltage capacitors connected from the output side ground plane to Vpos
and Vneg. An attempt was made to discharge to the RJ-45 pins, but the discharge was always to the shield
indicating that surging the shield is an appropriate test method.
The ESD gun was used in contact mode and the ESD pulses were applied in both polarities in 500 V increments up
to 9 kV. Above 9 kV, contact mode is not supported with the ESD gun; so, air discharge mode was used, again
increasing the voltage in 500 V steps up to the maximum available voltage of 16.5 kV in both polarities. After each
voltage increment, the board was tested and was not damaged. The 15 kV test was repeated 10 times for each
polarity, again with no damage observed after each test.
2 Rev. 0.2



Silicon Laboratories AN315
AN315
4.3. Telephony Voltages
IEEE STD™ 802.3-2005 also specifies that the application of telephony ringing of up to 56 VDC plus ac with a
peak of up to 175 V applied through 400 Ω source shall not result in a safety hazard.
Continuous application of such a large signal will eventually result in a device failure due to the high power present
at the clamp. Si3400 devices tested in this condition survive over one second and then eventually fail in a shorted
condition, which does not present a safety hazard. However, according to Telecordia GR1089 October 2002 7.5.2
and Figure 7-6, the approximately 300 mA peak current that results from this test requires that a "ring trip" be
detected and the ringing be removed within 0.1 seconds. This means that when exposed to even a very severe
fault condition of ringing directly applied, the Si3400 PD will not be damaged.
4.4. Cable Discharge
It is possible for the conductors in an Ethernet cable to develop a static charge, for example, by being dragged
www.DataSheeat4cUro.csosmcarpeting before being plugged in. While there is no standards-based test for this, a uniform test procedure
has been described[1].
A Si3400 PD evaluation board was tested using this procedure with the test diagram shown in Figure 2.
1 meter
Cat 5
48Vdc
Junction block
20 cm
Cat 5
Si3400
Isolated
EVB
25 ft cat 6 cable all pairs tied
together and connected to HyPot
HyPot tester
Associated
Research Inc
3565D
Load
Box
Earth
ground
Figure 2. Test Diagram
Test procedure:
1. Verify board functionality with 48 VDC Supply.
2. Unplug 1 m cable from junction block.
3. Charge 25 ft cable with HyPot tester at 1000 V.
4. Plug 25 ft cable into junction block with HyPot tester connected.
5. Unplug 25 ft cable while HyPot tester is still putting out voltage.
6. Plug in 48 V supply through 1 m cable.
7. Verify board functionality.
8. Repeat steps 2-7 testing twice at 1000 V and twice at each voltage above 1000 V in 500 V increments.
Rev. 0.2
3







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