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TC35273 Dataheets PDF



Part Number TC35273
Manufacturers Toshiba Semiconductor
Logo Toshiba Semiconductor
Description MPEG-4 Audiovisual LSI
Datasheet TC35273 DatasheetTC35273 Datasheet (PDF)

Preliminary TOSHIBA MPEG-4 Audiovisual LSI MPEG-4 Audiovisual Codec LSI TC35273 TC35273 Tentative Technical Data Sheet MPEG-4 Audiovisual LSI Features www.DataSheet4U.com U TC35273 is an MPEG-4 audiovisual codec LSI which supports 3GPP 3G-324M video telephony system. MPEG-4 video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T H.223 are executed concurrently at around 70MHz clock rate. U Three signal processing units, an MPEG-4 video codec.

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Preliminary TOSHIBA MPEG-4 Audiovisual LSI MPEG-4 Audiovisual Codec LSI TC35273 TC35273 Tentative Technical Data Sheet MPEG-4 Audiovisual LSI Features www.DataSheet4U.com U TC35273 is an MPEG-4 audiovisual codec LSI which supports 3GPP 3G-324M video telephony system. MPEG-4 video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T H.223 are executed concurrently at around 70MHz clock rate. U Three signal processing units, an MPEG-4 video codec, a speech codec / audio decoder, and a multiplex / demultiplex unit, are integrated on a single chip. P-FBGA201-1515-0.80A5 U A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing units. The embedded DRAM helps to reduce power consumption without performance degradation. U Each signal processing unit consists of a 16-bit RISC processor and dedicated hardware accelerators so as to bring programmability, high performance and low power consumption. Firmware programs for the RISCs are downloaded into the embedded DRAM before starting operation. Various applications are performed by choosing an appropriate firmware. General host interface are adopted in order to support various host CPU. 2.5x to 6x of PLL is integrated on the chip for easy system integration. U U U • TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. • The products described in this document are subject to foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. TOSHIBA Confidential 1/23 Version 0.90 2000-4-27 Preliminary • MPEG-4 Audiovisual Codec LSI TC35273 The circuit contained herein is presented only as a guide for the applications, and it is not guaranteed. www.DataSheet4U.com TOSHIBA Confidential 2/23 Version 0.90 2000-4-27 Preliminary 1. Functional Specifications 1.1 MPEG-4 Video Codec U MPEG-4 Audiovisual Codec LSI TC35273 ISO MPEG-4 International Standard Simple Profile @Level 1 is supported. Encoding and decoding with QCIF (176 x 144 pixel) at 15 frames per second are executed. YCbCr 4:2:2 8bit digital camera input. A CMOS camera or an NTSC decoder is connected. Temporal filter and size conversion for pre-filter function. YCbCr 4:2:2 8bit digital display output. An NTSC encoder or an LCD controller is connected. Size conversion and de-blocking filter for post-filter function. U U U U www.DataSheet4U.com 1.1.1. Speech Codec / Audio Decoder U U U U U U AMR Speech Codec at 8kbps with CS-ACELP.* ITU-T G.729 speech codec at 8Kbps with CS-ACELP.* ITU-T G.723.1 speech codec at 5.3kbp with ACELP, or 6.3kbps with MP-MLQ.* Stereo Twin-VQ audio decoder at 96kbps with up to 44.1-kHz sampling frequency.* ISO/IEC 13818-7 AAC LC audio decoder at 144kbps with up to 48-kHz sampling frequency.* PCM stereo or monoral sound input/output. An external microphone and a speaker are connected via DAC and ADC, respectively. 1.1.2. Multiplexer/Demultiplexer U Multiplexing and demultiplexing with ITU-T H.223 and H.223 Annex A,B protocol at 32Kbps 384Kbps.* Demultiplexing with ITU-T H.222.0 / ISO/IEC13818-1 at 32Kbps 1024Kbps.* Bitstream input/output via a network serial interface. U U * In order to run this LSI as an MEPG-4 audiovisual LSI, Specified firmware programs have to be obtained in advance TOSHIBA Confidential 3/23 Version 0.90 2000-4-27 Preliminary 1.2. System configuration. and 12-Mbit DRAM are integrated in a single chip. MPEG-4 Audiovisual Codec LSI TC35273 Fig. 1 illustrates a block diagram of this LSI. Three signal processing core, peripheral interfaces, Bitstream input/output are performed via a network interface in the Mux/Demux core. A Microphone and a speaker can be connected to a PCM interface in a speech/audio core via external DAC and ADC. TOSHIBA CMOS camera is connected to a camera interface via a camera DSP “TC90A5.


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