Document
Features
www.DataSheet4U.com • Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
• In-System Programmable (ISP) via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX™ Devices, • • • • • • • • •
Stratix™, Lattice Semiconductor® (ORCA®) FPGAs, Spartan®, Virtex™ FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 44-lead PLCC Package Emulation of Atmel’s AT24CXXX Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System Reconfiguration Fast Serial Download Speeds up to 33 MHz Endurance: 10,000 Write Cycles Typical LHF Package Available (Lead and Halide Free)
FPGA Configuration Flash Memory AT17F32
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17F Series device is packaged in the 44-lead PLCC, see Table 11. The AT17F Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
Package 44-lead PLCC
AT17F Series Packages
AT17F32 Yes
3393C–CNFG–6/05
2. Pin Configuration
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44-lead PLCC
NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC 6 5 4 3 2 1 44 43 42 41 40
2
AT17F32
3393C–CNFG–6/05
NC RESET/OE PAGESEL0 CE NC NC GND PAGESEL1 NC CEO/A2 NC
18 19 20 21 22 23 24 25 26 27 28
NC NC NC NC NC NC NC NC NC NC NC
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
NC NC NC NC NC NC NC NC NC NC READY
AT17F32
3. Block Diagram
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READY
Power-on Reset
Reset
Clock/Oscillator Logic
CLK
PAGE_EN PAGESEL0 PAGESEL1
Config. Page Select
CEO(A2) Serial Download Logic
2-wire Serial Programming
DATA
Flash Memory
CE/WE/OE Data Address
CE Control Logic RESET/OE SER_EN
4. Device Description
The control signals for the configuration memory device (CE, RESET/OE, and CLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
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3393C–CNFG–6/05
5. Pin Description
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Table 5-1.
Pin Description
AT17F32
Name DATA CLK PAGE_EN PAGESEL0 PAGESEL1 RESET/OE CE GND CEO A2 READY SER_EN VCC
I/O I/O I I I I I I – O
44 PLCC 2 5 1 20 25 19 21 24 27
I O I – 29 41 44
5.1
DATA(1)
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2
CLK(1)
Clock input. Used to increment the internal address and bit counter for reading and programming.
5.3
PAGE_EN(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download address space is partitioned into 4 equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be remain Low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
1. This pin has an internal 20 KΩ pull-up resistor. 2. This pin has an internal 30 KΩ pull-down resistor.
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AT17F32
3393C–CNFG–6/05
AT17F32
5.4 PAGESEL[1:0](2)
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Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial configuration download. The address space for each of the pages is shown in Table 5-2. When SER_EN is Low (ISP mode) these pins have no effect. Table 5-2. Address Space
AT17F32 (32 Mbits) 000000 – 07FFFFh 080000 – 0FFFFFh 100000 – 17FFFFh 180000 – 1FFFFFh 000000 – 1FFFFFh
Paging Decodes PAGESEL = 00, PAGE_EN = 1 PA.