Document
Features
www.DataSheet4U.com • Programmable 33,554,432 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• 3.3V Output Capability • 5V Tolerant I/O Pins • Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Altera® FLEX®, Excalibur™, Stratix™, Cyclone™ and APEX™ Devices Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 44 PLCC Packages Emulation of Atmel’s AT24Cxxx Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding 4 Individual Bit Stream Files Allowing Simple System Reconfiguration • Endurance: 10,000 Write Cycles Typical • Green (Lead and Halide-Free/ROHS Compliant) Package Options Available
• • • • • • • • •
FPGA Configuration Flash Memory AT17F32A
1. Description
The AT17FxxA Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17FxxA Series device is packaged in the 44-lead PLCC see Table 1-1. The AT17FxxA Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17FxxA Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
Package 44-lead PLCC
AT17FxxA Series Packages
AT17F32A Yes
3489C–CNFG–08/07
2. Pin Configuration
www.DataSheet4U.com
44-lead PLCC
6 5 4 3 2 1 44 43 42 41 40
NC NC NC NC DATA PAGE_EN NC NC NC VCC NC
2
AT17F32A
3489C–CNFG–08/07
NC GND PAGESEL0 NC NC NC NC NC NC NC nCASC/A2
18 19 20 21 22 23 24 25 26 27 28
NC DCLK NC NC NC NC NC NC NC RESET/OE nCS
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
NC SER_EN NC NC READY NC PAGESEL1 NC NC NC NC
AT17F32A
3. Block Diagram
www.DataSheet4U.com
READY
Power-on Reset
Reset
Clock/Oscillator Logic
DCLK
PAGE_EN PAGESEL0 PAGESEL1
Config. Page Select
nCASC(A2) Serial Download Logic
2-wire Serial Programming
DATA
Flash Memory
CE/WE/OE Data Address
nCS Control Logic RESET/OE SER_EN
4. Device Description
The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17FxxA Series Configurator. If nCS is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequen.