AT697E

Features www.DataSheet4U.com SPARC V8 High Performance Low-power 32-bit Architecture – LEON2-FT 1.0.13 compliant – 8 Register Windows Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache – 32 kbyte Multi-sets Instruction Cache On-chip Peripherals: – Memory Interface PROM Controller SRAM Controller SDRAM Controller – Timers Two 24-bit Timers Watchdog Timer – Two 8-bit UARTs – Interrupt Controller with 4 External Programmable Inputs – 32 Parallel I/O Interface – 33MHz PCI Interface Compliant with 2.2 PCI Specification Integrated 32/64-bit IEEE 754 Floating-point Unit Fault Tolerance by Design – Full Triple Modular Redundancy (TMR) – EDAC Protection – Parity Protection Debug and Test Facilities – Debug Support Unit (DSU) for Trace and Debug – IEEE 1149.1 JTAG Interface – Four Hardware Watchpoints Speed Optimized Code RAM Interface 8, 16 and 40-bit boot-PROM (Flash) Interface Possibilities Clock: 0MHz up to 100MHz Core consumption: 1W Performance: 100 MIPS Operating range – Voltages 3.3V +/- 0.30V for I/O 1.8V +/- 0.15V for Core – Temperature -55°C to 125°C Radiation Performance – Total dose radiation capability (parametric & functional): 100Krads (Si) (target) – SEU event rate better than 1 E-5 error/device/day (target) – Latch up immunity better than 70 MeV.cm²/mg Package MCGA 349 Mass: 9g Rad-Hard 32 bit SPARC V8 Processor AT697E Advance Information Summary Rev. 4226BS–AERO–01/05 Note: This is a ...