IDT72V3636

www.DataSheet4U.com 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 IDT72V3626 IDT72V3636 IDT72V3646 .EATURES: Memory storage capacity: IDT72V3626–256 x 36 x 2 IDT72V3636–512 x 36 x 2 IDT72V3646–1,024 x 36 x 2 Clock frequencies up to 100 MHz (6.5ns access time) Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits) 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRC flag functions) Programmable Almost-Empty and Almost-Full flags; each has three default offsets (8, 16 and 64) Serial or parallel programming of partial flags Big- or Little-Endian format for word and byte bus sizes Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA, CLKB and CLKC may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin and functionally compatible versions of 5V operating IDT723626/723636/723646 Industrial temperature range (–40°C to +85°C) is available .UNCTIONAL BLOCK DIAGRAM MBF1 Mail...