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K7N403601M Dataheets PDF



Part Number K7N403601M
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description (K7N401801M / K7N403601M) 128Kx36 & 256Kx18 Pipelined NtRAM-TM
Datasheet K7N403601M DatasheetK7N403601M Datasheet (PDF)

K7N403601M K7N401801M www.DataSheet4U.com 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed tCD,tOE from 4.0ns to 4.2ns at -75 2. Changed DC condition at Icc and parameters ISB1 ; from 10mA to 30mA, ISB2 ; from 10mA to 30mA. Add VDDQ Supply voltage( 2.5V I/O ) Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O. Final spec Release. Remove VDDQ Supply voltage( 2.5V I/O ) Add VDDQ.

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Document
K7N403601M K7N401801M www.DataSheet4U.com 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAM TM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed tCD,tOE from 4.0ns to 4.2ns at -75 2. Changed DC condition at Icc and parameters ISB1 ; from 10mA to 30mA, ISB2 ; from 10mA to 30mA. Add VDDQ Supply voltage( 2.5V I/O ) Changed VOL Max value from 0.2V to 0.4V at 2.5V I/O. Final spec Release. Remove VDDQ Supply voltage( 2.5V I/O ) Add VDDQ Supply voltage( 2.5V I/O ) Draft Date July.06. 1998 Oct. 10 . 1998 Remark Preliminary Preliminary 0.2 0.3 1.0 2.0 3.0 Dec. 10. 1998 Dec. 23. 1998 Jan. 29. 1999 Feb. 25. 1999 May. 13. 1999 Preliminary Preliminary Final Final Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- May 1999 Rev 3.0 K7N403601M K7N401801M www.DataSheet4U.com 128Kx36 & 256Kx18 Pipelined NtRAMTM 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM GENERAL DESCRIPTION The K7N403601M and K7N401801M are 4,718,592 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incomming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock. The K7N403601M and K7N401801M are implemented with SAMSUNG ′s high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. FEATURES • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention • Α interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • TTL-Level Three-State Outputs. • 100-TQFP-1420A Package. FAST ACCESS TIMES PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol -15 -13 -10 Unit tCYC tCD tOE 6.7 7.5 10 ns ns ns 3.8 4.2 5.0 3.8 4.2 5.0 LOGIC BLOCK DIAGRAM LBO A [0:16]or A [0:17] ADDRESS REGISTER A2~A16 or A2 ~A17 A0 ~A1 BURST ADDRESS COUNTER A′0~A′1 128Kx36 , 256Kx18 MEMORY ARRAY CLK CKE K WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER CONTROL LOGIC K DATA-IN REGISTER DATA-IN REGISTER K CS1 CS2 CS2 ADV WE BWx (x=a,b,c,d or a,b) OE ZZ DQa0 ~ DQd 7 or DQa0 ~ DQb8 DQPa ~ DQPd 36 or 18 CONTROL REGISTER CONTROL LOGIC K OUTPUT REGISTER BUFFER NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung, and its architecture and functionalities are supported by NEC and Toshiba. -2- May 1999 Rev 3.0 K7N403601M K7N401801M PIN CONFIGURATION(TOP VIEW) www.DataSheet4U.com BWd BWb 128Kx36 & 256Kx18 Pipelined NtRAMTM BWa BWc CKE ADV N.C. N.C. 83 CLK CS1 CS2 CS2 VDD VSS WE OE A6 A7 A8 82 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 81 A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 N.C. N.C. N.C. N.C. VDD A5 A4 A3 A2 A1 A0 A10 A11 A12 A13 A14 A15 PIN NAME SYMBOL A0 - A 16 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~P d VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 14,15,16,41,65,66,91 17,40,67,90 38,39,42,43,83,84 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 4,11,20,27,54,61,70,77 5,10,21,26,55,60,71,76 ADV WE CLK CKE CS1 CS2 CS2 BWx(x=a,b,c,d) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control LBO VSS Output Power Supply (2.5V or 3.3V) Output Ground Notes : 1. The pin 83 is reserved for address bit for the 8Mb NtRAM. 2. A0 and A1 are.


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