Document
K7N403609B K7N401809B
www.DataSheet4U.com
128Kx36 & 256Kx18 Pipelined NtRAMTM
Document Title
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
Revision History
Rev. No. 0.0 0.1 History 1. Initial document. 1. Changed DC parameters Icc ; from 470mA to 400mA at -25, from 440mA to 360mA at -22, from 400mA to 330mA at -20, from 370mA to 310mA at -18, ISB ; from 180mA from 170mA from 160mA from 150mA ISB1 ; from 100mA 0.2 1.0 to to to to to 160mA at -25, 155mA at -22, 150mA at -20, 140mA at -18, 80mA Aug. 11. 2001 Nov. 15. 2001 Preliminary Final Draft Date May. 15. 2001 June. 12. 2001 Remark Preliminary Preliminary
1. Add x32 org. and industrial temperature 1. Final spec release 2. Changed Pin Capacitance - Cin ; from 5pF to 4pF - Cout ; from 7pF to 6pF 1. Remove x32 organization. 2. Remove -25/-22 speed bin
2.0
Nov. 17. 2003
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov. 2003 Rev 2.0
K7N403609B K7N401809B
www.DataSheet4U.com
128Kx36 & 256Kx18 Pipelined NtRAMTM
4Mb NtRAM Pipelined Ordering Information
Org. Part Number K7N401801B-QC(I)13 256Kx18 K7N401809B-QC(I)20 K7N403601B-QC(I)13 Pipelined Pipelined 3.3 3.3 200 MHz 133 MHz Q :100TQFP 128Kx36 K7N403609B-QC(I)20 Pipelined 3.3 200 MHz Mode Pipelined VDD 3.3 Speed FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) 133 MHz C (Commercial Temperature Range) I: (Industrial Temperature Range) PKG Temp
-2-
Nov. 2003 Rev 2.0
K7N403609B K7N401809B
www.DataSheet4U.com
128Kx36 & 256Kx18 Pipelined NtRAMTM
128Kx36 & 256Kx18-Bit Pipelined NtRAMTM
GENERAL DESCRIPTION
The K7N403609B and K7N401809B are 4,718,592 bits Synchronous Static SRAMs. The NtRAMTM, or No Turnaround Random Access Memory utilizes all the bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation and provides increased timing flexibility for incomming signals. For read cycles, pipelined SRAM output data is temporarily stored by an edge trigered output register and then released to the output bufferes at the next rising edge of clock. The K7N403609B and K7N401809B are implemented with SAMSUNG′s high performance CMOS technology and is available in 100pin TQFP packages. Multiple power and ground pins minimize ground bounce. • VDD=3.3V+0.165V/-0.165V Power Supply. • VDDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O. • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no datacontention. • Α interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • TTL-Level Three-State Outputs. • 100-TQFP-1420A Package. • Operating in commeical and industrial temperature range.
FEATURES
FAST ACCESS TIMES
PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -20 5.0 2.8 2.8 Unit ns ns ns
LOGIC BLOCK DIAGRAM
A [0:16]or A [0:17]
LBO ADDRESS REGISTER A2~A16 or A2~A17 A0~A1
BURST ADDRESS COUNTER
A′0~A′1 128Kx36 , 256Kx18 MEMORY ARRAY
CLK CKE CS1 CS2 CS2 ADV WE
K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
BWx (x=a,b,c,d or a,b) OE ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb8 DQPa ~ DQPd
CONTROL LOGIC
K
DATA-IN REGISTER DATA-IN REGISTER
K
CONTROL REGISTER
CONTROL LOGIC
K
OUTPUT REGISTER BUFFER
36 or 18
NtRAMTM and No Turnaround Random Access Memory are trademarks of Samsung,
-3-
Nov. 2003 Rev 2.0
K7N403609B K7N401809B
PIN CONFIGURATION(TOP VIEW) www.DataSheet4U.com
BWd BWb
128Kx36 & 256Kx18 Pipelined NtRAMTM
BWa
BWc
CKE
ADV
N.C.
A6
N.C. 83
CLK
CS1
CS2
CS2
VDD
VSS
WE
OE
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
81
A9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
N.C.
N.C.
N.C.
N.C.
VSS
A5
A4
A3
A2
A1
A0
A10
A12
A13
A14
A15
LBO
VDD
PIN NAME
SYMBOL A0 - A16 PIN NAME Address Inputs TQFP PIN NO. 32,33,34,35,36,37 44,45,46,47,48,49 50,81,82,99,100 85 88 89 87 98 97 92 93,94,95,96 86 64 31 SYMBOL VDD VSS N.C. DQa0~a7 DQb0~b7 DQc0~c7 DQd0~d7 DQPa~Pd VDDQ VSSQ PIN NAME Power Supply(+3.3V) Ground No Connect Data Inputs/Outputs TQFP PIN NO. 14,15,16,4.