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ASM5P2309A Dataheets PDF



Part Number ASM5P2309A
Manufacturers Alliance Semiconductor Corporation
Logo Alliance Semiconductor Corporation
Description (ASM5P2305A / ASM5P2309A) 3.3V Zero Delay Buffer
Datasheet ASM5P2309A DatasheetASM5P2309A Datasheet (PDF)

September 2005 www.DataSheet4U.com ASM5P2309A ASM5P2305A 3.3V Zero Delay Buffer rev 1.6 General Features ƒ ƒ ƒ 15MHz to 133MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs. ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output-output skew less than 250pS. Device-device skew less than 700pS. One input drives 9 outputs, grouped as 4 + 4 + 1(ASM5P2309A). One input drives 5 outputs (ASM5P2305A). Less than 200 pS cycle-to-cycle jitter is compatible .

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September 2005 www.DataSheet4U.com ASM5P2309A ASM5P2305A 3.3V Zero Delay Buffer rev 1.6 General Features ƒ ƒ ƒ 15MHz to 133MHz operating range, compatible with CPU and PCI bus frequencies. Zero input - output propagation delay. Multiple low-skew outputs. ƒ ƒ ƒ ƒ ƒ ƒ ƒ Output-output skew less than 250pS. Device-device skew less than 700pS. One input drives 9 outputs, grouped as 4 + 4 + 1(ASM5P2309A). One input drives 5 outputs (ASM5P2305A). Less than 200 pS cycle-to-cycle jitter is compatible with Pentium® based systems. Test Mode to bypass PLL (ASM5P2309A only, Refer Select Input Decoding Table). Available in 16pin 150-mil SOIC, 4.4 mm TSSOP (ASM5P2309A), and in 8pin 150-mil SOIC package (ASM5P2305A). ƒ 3.3V operation, advanced 0.35µ CMOS technology. 133MHz frequencies, and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The ASM5P2309A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. Multiple ASM5P2309A and ASM5P2305A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700pS. All outputs have less than 200pS of cycle-to-cycle jitter. The input and output propagation delay is guaranteed to be less than 350pS, and the output to output skew is guaranteed to be less than 250pS. The ASM5P2309A and the ASM5P2305A are available in two different configurations, as shown in the ordering information table. The ASM5P2305A-1/ ASM5P2309A-1 is the base part. The ASM5P2305A-1H/ ASM5P2309A-1H is the high drive version of the -1 and its rise and fall times are much faster than -1 part. Functional Description ASM5P2309A is a versatile, 3.3V zero-delay buffer designed to distribute high-speed clocks. It accepts one reference input and drives out nine low-skew clocks. It is available in a 16-pin package. The ASM5P2305A is the eight-pin version of the ASM5P2309A. It accepts one reference input and drives out five low-skew clocks. The -1H version of the ASM5P23XXA operates at up to Block Diagram PLL PLL CLKOUT CLK1 CLK2 CLK3 S2 S1 REF MUX CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 Select Input Decoding CLKB1 CLKB2 CLKB3 REF ASM5P2305A CLK4 ASM5P2309A CLKB4 Alliance Semiconductor 2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. September 2005 www.DataSheet4U.com ASM5P2309A ASM5P2305A rev 1.6 Select Input Decoding for ASM5P2309A S2 0 0 1 1 Notes: 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and the output. S1 0 1 0 1 Clock A1 - A4 Three-state Driven Driven Driven Clock B1 - B4 Three-state Three-state Driven Driven CLKOUT1 Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shut-Down N N Y N Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero-input-output delay. 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 2 of 20 September 2005 www.DataSheet4U.com ASM5P2309A ASM5P2305A rev 1.6 Pin Configuration REF 1 CLKA1 CLKA2 VDD GND 2 3 4 5 16 CLKOUT 15 CLKA4 14 CLKA3 13 VDD 12 GND 11 CLKB4 10 CLKB3 9 S1 ASM5P2309A CLKB1 6 CLKB2 7 S2 8 REF CLK2 CLK1 GND 1 2 8 7 CLKOUT CLK4 VDD CLK3 ASM5P2305A 3 4 6 5 Pin Description for ASM5P2309A Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name REF 2 3 3 Description Input reference frequency, 5V tolerant input Buffered clock output, bank A Buffered clock output, bank A 3.3V supply Ground Buffered clock output, bank B Buffered clock output, bank B Select input, bit 2 Select input, bit 1 CLKA1 CLKA2 VDD GND CLKB13 CLKB2 S2 S1 4 4 3 3 3 CLKB3 CLKB4 GND VDD CLKA3 CLKA4 Buffered clock output, bank B Buffered clock output, bank B Ground 3.3V supply 3 3 3 Buffered clock output, bank A Buffered clock output, bank A Buffered output, internal feedback on this pin CLKOUT 3.3V Zero Delay Buffer Notice: The information in this document is subject to change without notice. 3 of 20 September 2005 www.DataSheet4U.com ASM5P2309A ASM5P2305A rev 1.6 Pin Description for ASM5P2305A Pin # 1 2 3 4 5 6 7 8 Notes: 2. Weak pull-down. 3. Weak pull-down on all outputs. 4. Weak pull-up on these inpu.


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