ADEBC2808 SO-DIMM Datasheet

ADEBC2808 Datasheet, PDF, Equivalent


Part Number

ADEBC2808

Description

PC-133 SDRAM Unbuffered SO-DIMM

Manufacture

A-Data Technology

Total Page 9 Pages
Datasheet
Download ADEBC2808 Datasheet


ADEBC2808
A-Data
ADEBC2808
PC-133 SDRAM Unbuffered SO-DIMM
www.DataSheet4U.com
32Mx64bits SDRAM DIMM based on 16Mx16, 4Bank, 8K Refresh, 3.3V SDRAM
General Description
Features
The ADEBC2808 is 32Mx64 bits Synchronous DRAM
Modules, The modules are composed of eight
16Mx16 bits CMOS Synchronous DRAMs in TSOP-II
400mil 54pin package and one 2Kbit EEPROM in 8pin
TSSOP(TSOP) package on a 144pin glass–epoxy
PC-133 support
Auto refresh and self refresh
8192 refresh cycles / 64ms
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL
printed circuit board.
The A-Data is a Dual In-line Memory Module and is
intended for mounting onto 144-pins edge connector
sockets. Fully synchronous operation referenced to
the positive edge of the clock. All inputs and outputs
interface
Data mask function by DQM
Serial Presence Detect with EEPROM
Module bank : two physical bank
PCB : BSS960,Height (31.75mm),double
are synchronized with the rising edge of the clock.
sided component, Six layers
The data paths are internally pipelined to achieve very
high bandwidth.
Ordering Information.
Part No.
ADEBC2808
Frequency
133Mhz
Bank
4 Banks
Ref.
8K
Package
TSOP II
Pin Assignment
FRONT SIDE
BACK SIDE
PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME
1 VSS 19 DQ7 37 DQ8 55 VSS 73 NC 91 VSS 109 A9 127 DQ27
2 VSS 20 DQ39 38 DQ40 56 VSS 74 CK1 92 VSS 110 BA1 128 DQ59
3 DQ0 21 VSS 39 DQ9 57 NC 75 VSS 93 DQ20 111 A10/AP 129 VDD
4 DQ32 22 VSS 40 DQ41 58 NC 76 VSS 94 DQ52 112 A11 130 VDD
5 DQ1 23 DQM0 41 DQ10 59 NC 77 NC 95 DQ21 113 VDD 131 DQ28
6 DQ33 24 DQM4 42 DQ42 60 NC 78 NC 96 DQ53 114 VDD 132 DQ60
7 DQ2 25 DQM1 43 DQ11 61 CK0 79 NC 97 DQ22 115 DQM2 133 DQ29
8 DQ34 26 DQM5 44 DQ43 62 CKE0 80 NC 98 DQ54 116 DQM6 134 DQ61
9 DQ3 27 VDD 45 VDD 63 VDD 81 VDD 99 DQ23 117 DQM3 135 DQ30
10 DQ35 28 VDD 46 VDD 64 VDD 82 VDD 100 DQ55 118 DQM7 136 DQ62
11 VDD 29 A0 47 DQ12 65 /RAS 83 DQ16 101 VDD 119 VSS 137 DQ31
12 VDD 30 A3 48 DQ44 66 /CAS 84 DQ48 102 VDD 120 VSS 138 DQ63
13 DQ4 31 A1 49 DQ13 67 /WE 85 DQ17 103 A6 121 DQ24 139 VSS
14 DQ36 32 A4 50 DQ45 68 CKE1 83 DQ49 104 A7 122 DQ56 140 VSS
15 DQ5 33 A2 51 DQ14 69 /CS0 87 DQ18 105 A8 123 DQ25 141 **SDA
16 DQ37 34 A5 52 DQ46 70 A12 88 DQ50 106 BA0 124 DQ57 142 **SCL
17 DQ6 35 VSS 53 DQ15 71 /CS1 89 DQ19 107 VSS 125 DQ26 143 VDD
18 DQ38 36 VSS 54 DQ47 72 *A13 90 DQ51 108 VSS 126 DQ58 144 VDD
* These pins are not used in this module.
** These pins should be NC in the system which does not support SPD.
Rev 1 April, 2001
1

ADEBC2808
A-Data
www.DataSheet4U.com
Pin Description
PIN NAME
CK0~1 System Clock
CKE0~1 Clock Enable
/CS0~1 Chip Select
A0~A12 Address
BA0~BA1 Banks Select
DQ0~DQ63 Data
DQM0~7 Data Mask
/RAS Row Address Strobe
/CAS Column Address Strobe
/WE Write Enable
VDD/VSS Power Supply/Ground
SDA Serial data I/O
SCL Serial clock
SA0~2 Address in EEPROM
NC No Connection
ADEBC2808
FUNCTION
Active on the positive edge to sample all inputs.
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
Disables or Enables device operation by masking or enabling all input
except CK, CKE and L(U)DQM
Row / Column address are multiplexed on the same pins.
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Makes data output Hi-Z,
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS low
Enables write operation and row recharge.
Power and Ground for the input buffers and the core logic.
EEPROM serial data I/O
EEPROM clock input
EEPROM address input
This pin is recommended to be left No Connection on the device.
Rev 1 April, 2001
2


Features A-Data www.DataSheet4U.com ADEBC2808 P C-133 SDRAM Unbuffered SO-DIMM 32Mx64bi ts SDRAM DIMM based on 16Mx16, 4Bank, 8 K Refresh, 3.3V SDRAM General Descript ion The ADEBC2808 is 32Mx64 bits Synchr onous DRAM Modules, The modules are com posed of eight 16Mx16 bits CMOS Synchro nous DRAMs in TSOP-II 400mil 54pin pack age and one 2Kbit EEPROM in 8pin TSSOP( TSOP) package on a 144pin glass–epoxy printed circuit board. The A-Data is a Dual In-line Memory Module and is inte nded for mounting onto 144-pins edge co nnector sockets. Fully synchronous oper ation referenced to the positive edge o f the clock. All inputs and outputs are synchronized with the rising edge of t he clock. The data paths are internally pipelined to achieve very high bandwid th. Features •PC-133 support •Auto refresh and self refresh •8192 refre sh cycles / 64ms •Single 3.3±0.3V po wer supply •All device pins are compa tible with LVTTL interface •Data mask function by DQM •Serial Presence Detect with EEPROM •Module bank : two physic.
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