HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
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HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
ID...
Description
www.DataSheet4U.com
HIGH-SPEED 3.3V 64K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
IDT70V3389S
Features
True Dual-Port memory cells which allow simultaneous access of the same memory location x High-speed clock to data access – Commercial: 4.2/5/6ns (max.) – Industrial: 5/6ns (max) x Pipelined output mode x Counter enable and reset features x Dual chip enables allow for depth expansion without additional logic x Full synchronous operation on both ports – 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth) – Fast 4.2ns clock to data out – 1.8ns setup to clock and 0.7ns hold on all control, data, and
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address inputs @ 133MHz – Data input, address, byte enable and control registers – Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±150mV) power supply for core LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV) power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available for selected speeds Available in a 128-pin Thin Quad Plastic Flatpack (TQFP), 208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid Array
Functional Block Diagram
UBL LBL R/WL
B W 0 L B W 1 L B B WW 1 0 R R
UBR LBR R/WR
CE0L CE1L
CE0R CE1R
OEL Dout0-8_L Dout9-17_L Dout0-8_R Dout9-17_R
OER
64K x 18 MEMORY ARRAY
I/O0 L - I/O1 7 L CLKL
Din_L
Din_R
I/O0R - I/O17R CLKR
A15L A0L CNTRSTL ADSL C...
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