Document
Preliminary
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PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
DIE CONFIGURATION
65 mil
FEATURES
• • • • • • • • • 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100MHz – 200MHz (no PLL). Low Injection Power for crystal 50uW. Complementary outputs: CMOS, PECL or LVDS. Selectable OE Logic (enable high or enable low). Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in die form. Die thickness is 10 mil.
DNC
DNC
VDD
VDD
VDD
VDD
N/C
N/C
(1550,1475)
17 16
25
24
23
22
21
20
19
18
GNDBUF N/C LVDSB PECLB VDDBUF VDDBUF PECL LVDS OUTSEL^
XIN XOUT DNC
62 mil
26
27
Die ID: A1919-19B
15
28
14
13
DESCRIPTIONS
PLL520-20 is a VCXO IC specifically designed to pull high frequency fundamental crystals. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input.
DNC OE CTRL VCON
29
12
11 30
C502A
31 1 2 3 4 5 6 7 8
10 9
Reserved
Y
(0,0)
X
DIE SPECIFICATIONS
Name Value 62 x 65 mil GND 80 micron x 80 micron 10 mil Size Reverse side Pad dimensions Thickness
BLOCK DIAGRAM
OE VCON Oscillator X+ XQ Q
Amplifier w/ integrated varicaps
PLL520-20
OUTPUT SELECTION AND ENABLE
Pad #18 OUTSEL1 0 0 1 1 OE_SELECT (Pad #9) 0 1 (Default) Pad #25 OUTSEL0 0 1 0 1 OE_CTRL (Pad #30) 0 1 (Default) 0 (Default) 1 Selected Output High Drive CMOS Standard CMOS LVDS PECL (default) State Tri-state Output enabled Output enabled Tri-state
Pad #9, 18, 25: Bond to GND to set to “0”, bond to VDD to set to “1” No connection results to “default” setting through internal pull-up/-down. Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is “1” Logical states defined by CMOS levels if OE_SELECT is “0”
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
GND
Preliminary
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PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection
SYMBOL
V DD VI VO TS TA TJ
MIN.
V SS -0.5 V SS -0.5 -65 0
MAX.
4.6 V DD +0.5 V DD +0.5 150 70 125 260 2
UNITS
V V V °C °C °C °C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR
SYMBOL
F XIN C L (xtal) C0 C 0 /C 1 (xtal) RE AT cut AT cut
CONDITIONS
Parallel Fundamental Mode Die at VCON = 1.65V
MIN.
120
TYP.
MAX.
200
UNITS
MHz pF
4 3.5 250 30
pF Ω
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB 25
SYMBOL
T VCXOSTB
CONDITIONS
From power valid XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V at room temperature VCON = 0 to 3.3V
MIN.
180*
TYP.
10
MAX.
UNITS
ms ppm
± 100* 4 – 18* 4* 65 60 5*
ppm pF % ppm/V kΩ kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 03/03/05 Page 2
Preliminary
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PLL520-20
Low Phase Noise VCXO (for 100-200MHz Fundamental Crystals)
4. General Electrical Specifications PARAMETERS
Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
I DD V DD
CONDITIONS
PECL/LVDS
MIN.
3.13
TYP.
MAX.
100/80/40 3.47
UNITS
mA V % mA
@ 1.25V (LVDS) @ Vdd – 1.3V (PECL)
45 45
50 50 ± 50
55 55
5. Jitter specifications PARAMETERS
Period jitter RMS at 155MHz Period jitter peak-to-peak at 155MHz Accumulated jitter RMS at 155MHz Accumulated jitter peak-to-peak at 155MHz Random Jitter Integrated jitter RMS at 155MHz
Measured on Wavecrest SIA 3000
CONDITIONS
At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. “RJ” measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5 18.5 2.5 24 2.5 0.3
MAX.
20
.