PLL520-38

PLL520-38/-39 www.DataSheet4U.com PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal) PIN CONFIGURATION VDD XIN XOUT N/C N/C OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 N/C N/C GND CLKC VDD CLKT N/C N/C FEATURES 65MHz to 130MHz Fundamental Mode Crystal. Output range: 65MHz – 130MHz (no PLL). Low Injection Power for crystal 50uW. PECL (PLL520-38) or LVDS output (PLL520-39). Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3 QFN). PLL 520-3x DESCRIPTION The PLL520-38/-39 is a family of VCXO IC’s specifically designed to pull high frequency fundamental crystals from 65MHz to 130MHz, with selectable PECL or LVDS outputs.. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input. Their very low jitter makes them ideal for the most demanding timing requirements. VCON GND VDD VDD N/C 10 XIN XOUT N/C 12 13 14 15 16 1 11 N/C 9 8 7 6 5 GND CLKC VDD CLKT P520-3x 2 3 4 BLOCK DIAGRAM OE GND GND OE VCON Oscillator XIN XOUT Q Q Amplifier w/ integrated varicaps OUTPUT ENABLE LOGICAL LEVELS Part # PLL520-38 OE 0 (Default) 1 0 1 (Default) State Output enabled Tri-state Tri-state Output enabled PLL520-38/-39 PLL520-39 OE input: Logical states defined by PECL levels for PLL520-38 Logical states defined by CMOS levels for PLL520-39 47745 Fremont Blvd., Fremont, California 94538 Tel (510...