Document
Preliminary
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PLL520-70
CMOS Low Phase Noise VCXO (for 45-90MHz Fund Xtal)
DIE CONFIGURATION
65 mil (1550,1475)
19 18 17 16 25 26 24 23 22 21 20
FEATURES
• • • • • • • 45MHz to 90MHz Fundamental Mode Crystal. Output range: 45MHz – 90MHz (no PLL). CMOS outputs. Integrated variable capacitors. Supports 3.3V-Power Supply. Available in die form. Thickness 10 mil.
27
15
28
14
62 mil
13 29 12
11 30
DESCRIPTIONS
31
10 9 1 2 3 4 5 6 7 8
PLL520-70 is a VCXO IC specifically designed to pull frequency fundamental crystals from 45MHz to 90MHz, with CMOS outputs. Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input.
Y X
(0,0)
DIE SPECIFICATIONS
Name Size Reverse side Pad dimensions Thickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil
BLOCK DIAGRAM
OE
DRIVE_SEL AND OE_CTRL TABLE
VCON Oscillator Amplifier w/ X+ integrated varicaps XQ Pad #19 DRIVE_SEL 0 1 Pad #30 OE_CTRL 0 1 Output Drive High Drive CMOS Standard CMOS (default) State Tri-state Output enabled (default)
PLL520-70
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 8/26/02 Page 1
Preliminary
www.DataSheet4U.com
PLL520-70
CMOS Low Phase Noise VCXO (for 45-90MHz Fund Xtal)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection
SYMBOL
V DD VI VO TS TA TJ
MIN.
V SS -0.5 V SS -0.5 -65 -40
MAX.
7 V DD +0.5 V DD +0.5 150 85 125 260 2
UNITS
V V V °C °C °C °C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note : Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. Crystal Specifications PARAMETERS
Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency
SYMBOL
CX+ CXC0 γ OF
CONDITIONS
45MHz to 90MHz (VDD=3.3V)
MIN.
TYP.
MAX.
2 2
UNITS
pF
3.6 250 Fund. 45 90 MHz
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB 25
SYMBOL
T VCXOSTB
CONDITIONS
From power valid XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V at room temperature VCON = 0 to 3.3V
MIN.
200*
TYP.
10
MAX.
UNITS
ms ppm
± 100* 4 – 18* 5* 65 60 10*
ppm pF % ppm/V kΩ kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 8/26/02 Page 2
Preliminary
www.DataSheet4U.com
PLL520-70
CMOS Low Phase Noise VCXO (for 45-90MHz Fund Xtal)
4. General Electrical Specifications PARAMETERS
Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
I DD V DD
CONDITIONS
MIN.
3.13
TYP.
MAX.
40 3.47
UNITS
mA V % mA
@ 1.4V
45
50 ± 50
55
5. Jitter specifications PARAMETERS
Period jitter RMS Period jitter peak-to-peak Integrated jitter RMS
*: To be measured
CONDITIONS
77.76MHz 77.76MHz Integrated 12 kHz to 20 MHz at 77.76MHz
MIN.
TYP.
3.5* 24* 0.5*
MAX.
UNITS
ps ps ps
6. Phase noise specifications PARAMETERS
Phase Noise relative to carrier
FREQUENCY
77.76MHz
@10Hz
-75
@100Hz
-95
@1kHz
-125
@10kHz
-145
@100kHz
-155
UNITS
dBc/Hz
Note: Phase Noise at VCON = 0V – to be measured
7. CMOS Output Electrical Specifications PARAMETERS
Output High Voltage Output Low Voltage Output High Voltage at CMOS level Output drive current
SYMBOL
V OH V OL V OHC
CONDITIONS
I OH = -12mA (Standard drive) I LO = 12mA (Standard drive) I OH = -4mA (Standard drive) At TTL level (High drive) At TTL level (Standard drive)
MIN.
2.4
TYP.
MAX.
0.4
UNITS
V V V mA mA
V DD – 0.4 36 12 51 17
8. CMOS Switching Characteristics PARAMETERS
Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive)
SYMBOL
CONDITIONS
0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load
MIN.
TYP.
1.15 3.7 0.5 1.5
MAX.
UNITS
ns
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 8/26/02 Page 3
Preliminary
www.DataSheet4U.com
PLL520-70
CM.