Document
ICX055BL
www.DataSheet4U.com
Diagonal 6mm (Type 1/3) CCD Image Sensor for CCIR B/W Video Cameras
Description The ICX055BL is an interline CCD solid-state image sensor suitable for CCIR B/W video cameras. Compared with the current product ICX055AL, sensitivity is improved drastically through the adoption of Super HAD CCD technology. This chip features a field period readout system, and an electronic shutter with variable charge-storage time. Features • High sensitivity (+4dB at F8, +2dB at F1.2 compared with ICX055AL) • High saturation signal (+1dB compared with ICX055AL) • Low smear and low dark current • Excellent antiblooming characteristics • Continuous variable-speed shutter • Horizontal register: 5V drive • Reset gate: 5V drive
16 pin DIP (Plastic)
Pin 1 1
V 14 7 Pin 9 H 30
Optical black position Device Structure (Top View) • Interline CCD image sensor • Image size: Diagonal 6mm(Type 1/3) • Number of effective pixels: 500 (H) × 582 (V) approx. 290K pixels • Number of total pixels: 537 (H) × 597 (V) approx. 320K pixels • Chip size: 6.00mm (H) × 4.96mm (V) • Unit cell size: 9.8µm (H) × 6.3µm (V) • Optical black: Horizontal (H) direction: Front 7 pixels, Rear 30 pixels Vertical (V) direction: Front 14 pixels, Rear 1 pixel • Number of dummy bits: Horizontal 16 Vertical 1 (even field only) • Substrate material: Silicon
∗Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing newly
developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98225A99
ICX055BL
VOUT
VGG
VSS
GND
Vφ2
8
7
6
5
Vφ1
Vφ3
4
3
2
Vertical register
Horizontal register Note) 9 10 11 12 13 14 15 16 : Photo sensor
VL
GND
SUB
Pin Description Pin No. 1 2 3 4 5 6 7 8 Symbol Vφ4 Vφ3 Vφ2 Vφ1 GND VGG VSS VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock GND Output amplifier gate bias Output amplifier source Signal output Pin No. 9 10 11 12 13 14 15 16 Symbol VDD GND SUB VL RG NC Hφ1 Hφ2 Horizontal register transfer clock Horizontal register transfer clock Description Output amplifier drain supply GND Substrate (Overflow drain) Protective transistor bias Reset gate clock
Absolute Maximum Ratings Item Substrate voltage SUB – GND Supply voltage VDD, VOUT, VSS – GND VDD, VOUT, VSS – SUB Vφ1, Vφ2, Vφ3, Vφ4 – GND Vφ1, Vφ2, Vφ3, Vφ4 – SUB Ratings –0.3 to +55 –0.3 to +18 –55 to +10 –15 to +20 to +10 to +15 to +17 –17 to +17 –10 to +15 –55 to +10 –65 to +0.3 –0.3 to +30 –0.3 to +24 –0.3 to +20 –30 to +80 –10 to +60 Unit V V V V V V V V V V V V V V °C °C ∗1 Remarks
Vertical clock input voltage
Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins Hφ1, Hφ2 – Vφ4 Hφ1, Hφ2, RG, VGG – GND Hφ1, Hφ2, RG, VGG – SUB VL – SUB Vφ1, Vφ2, Vφ3, Vφ4, VDD, VOUT – VL RG – VL VGG, Vss, Hφ1, Hφ2 – VL Storage temperature Operating temperature *1 +27V (Max.) when clock width<10µs, clock duty factor<0.1%. –2–
VDD
Hφ 1
Hφ 2
RG
NC
Vφ4
1 Note
Block Diagram and Pin Configuration www.DataSheet4U.com (Top View)
ICX055BL
Bias Conditions
www.DataSheet4U.com
Item
Symbol VDD VGG VSS VSUB ∆VSUB VRGL ∆VRGL VL
Min. 14.55 1.75
Typ. 15.0 2.0
Max. 15.45 2.25
Unit V V
Remarks
Output amplifier drain voltage Output amplifier gate voltage Output amplifier source Substrate voltage adjustment range Fluctuation range after substrate voltage adjustment Reset gate clock voltage adjustment range Fluctuation range after reset gate clock voltage adjustment Protective transistor bias DC Characteristics Item Output amplifier drain current Input current Input current Symbol IDD IIN1 IIN2 Min. Typ. 3
Grounded with 680Ω resistor 9.0 –3 1.0 –3 ∗2 18.5 +3 4.0 +3 V % V %
±5% ∗1 ∗1
Max.
Unit mA
Remarks ∗3 ∗4
1 10
µA µA
∗1 Indications of substrate voltage (VSUB) · reset gate clock voltage (VRGL) setting value. The setting values of substrate voltage and reset gate clock voltage are indicated on the back of the image sensor by a special code. Adjust substrate voltage (VSUB) and reset gate clock voltage (VRGL) to the indicated voltage. Fluctuation range after adjustment is ±3%. VSUB code VRGL code one character indication one character indication ↑ ↑ VRGL code VSUB code Code and optimal setting correspond to each other as follows. 1 2 3 4 5 6 7
VRGL code Optimal setting VSUB code Optimal setting
1.0 1.5 2.0 2.5 3.0 3.5 4.0 E f G h J K L m N P Q R S T U V W X Y Z
9.0 9.5 10.0 10.5 1.