HYB25D512400DF

July 2008 www.DataSheet4U.com HYB25D512400D[E/F/T] HY[B/I]25D512800D[C/E/F/T](L) HY[B/I]25D512160D[C/E/F/T](L) 5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M DDR SDRAM Internet Data Sheet Rev. 1.01 Internet Data Sheet www.DataSheet4U.com HY[B/I]25D512[40/80/16]0D[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM Revision History: Rev. 1.01, 2008-07 All Page 29 Page 33 All Adapted internet edition Changed tCK.MAX at CL=3 for -5 speed Added new IDD values New data sheet Previous Revision: Rev. 1.00, 2007-08 Previous Revision: Rev. 0.5, 2007-08 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_A4, 4.20, 2008-01-25 08102007-5IZ2-ENDV 2 Internet Data Sheet www.DataSheet4U.com HY[B/I]25D512[40/80/16]0D[C/E/F/T](L) 512-Mbit Double-Data-Rate SDRAM 1 Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics. 1.1 Features Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs...