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IRFR/U3711ZPbF

Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the Rds(on) of the

MOSFET, but these conduction losses are only about

one half of the total losses.

Power losses in the control switch Q1 are given

by;

Ploss = P +conduction P +switching Pdrive+ Poutput

This can be expanded and approximated by;

( )Ploss =

I2

rms

×

Rds(on )

⎛

+⎜I

⎝

×

Qgd

ig

× Vin

×

f ⎞⎟

⎠

⎛

+⎜I ×

⎝

Qgs 2

ig

× Vin

×

f ⎟⎞

⎠

( )+ Qg × Vg × f

+

⎛

⎝

Qoss

2

× Vin

×

f

⎞

⎠

This simplified loss equation includes the terms Qgs2

and Qoss which are new to Power MOSFET data sheets.

Qgs2 is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Qgs1 and Qgs2, can be seen from

Fig 16.

Qgs2 indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to Idmax at which time the drain voltage be-

gins to change. Minimizing Qgs2 is a critical factor in

reducing switching losses in Q1.

Qoss is the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Qoss is formed by the

parallel combination of the voltage dependant (non-

linear) capacitances Cds and Cdg when multiplied by

the power supply input buss voltage.

8

Synchronous FET

The power loss equation for Q2 is approximated

by;

Ploss

=

Pconduction

+

Pdrive

+

P*

output

( )Ploss =

I2

rms

×

Rds(on)

( )+ Qg × Vg × f

( )+ ⎛⎜ Qoss

⎝2

× Vin

×

f⎞

⎠

+

Qrr × Vin × f

*dissipated primarily in Q1.

For the synchronous MOSFET Q2, R is an im-

ds(on)

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q and re-

oss

verse recovery charge Qrr both generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V . As Q1 turns on and off there is

in

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Qgd/Qgs1 must be minimized to reduce the

potential for Cdv/dt turn on.

Figure A: Qoss Characteristic

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