Digital FET. FDG6313N Datasheet

FDG6313N Datasheet PDF, Equivalent


Part Number

FDG6313N

Description

Dual N-Channel Digital FET

Manufacture

Fairchild Semiconductor

Total Page 5 Pages
PDF Download
Download FDG6313N Datasheet


FDG6313N Datasheet
www.DataSheet4U.com
April 2002
FDG6313N
Dual N-Channel, Digital FET
General Description
These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
Features
25 V, 0.50 A continuous, 1.5 A peak.
RDS(ON) = 0.45 @ VGS= 4.5 V,
RDS(ON) =0.60 @ VGS= 2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
SC70-6
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
S2
G2
D1 .33
SC70-6
D2
G1
S1
1 or 4 *
2 or 5
3 or 6
* The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain/Output Current - Continuous
- Pulsed
PD
TJ,TSTG
ESD
Maximum Power Dissipation
(Note 1)
Operating and Storage Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100 pF / 1500 )
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient
FDG6313N
25
- 0.5 to +8
0.5
1.5
0.3
-55 to 150
6.0
415
6 or 3
5 or 2
4 or 1 *
Units
V
V
A
W
°C
kV
°C/W
FDG6313N Rev.A

FDG6313N Datasheet
Electrical Characteristics
www.DataSheet4U.com
(TA
=
25
OC
unless
otherwise
noted
)
Symbol
Parameter
Conditions
Min Typ Max Units
OFF CHARACTERISTICS
BVDSS
BVDSS/TJ
IDSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
IGSS Gate - Body Leakage Current
ON CHARACTERISTICS (Note 2)
VGS = 0 V, ID = 250 µA
ID = 250 µA, Referenced to 25oC
25
26
V
mV/oC
VDS = 20 V, VGS = 0 V
1 µA
TJ = 55°C
10 µA
VGS = 8 V, VDS = 0 V
100 nA
VGS(th)
VGS(th)/TJ
RDS(ON)
Gate Threshold Voltage
Gate Threshold Voltage Temp.Coefficient
Static Drain-Source On-Resistance
ID(ON) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
VDS = VGS, ID = 250 µA
ID = 250 µA, Referenced to 25oC
0.65 0.8
-2.6
VGS = 4.5 V, ID = 0.5 A
0.34
TJ =125°C
0.55
VGS = 2.7 V, ID = 0.2 A
0.44
VGS = 2.7 V, VDS = 5 V
0.5
VDS = 5 V, ID = 0.5 A
1.45
1.5 V
mV/oC
0.45
0.77
0.6
A
S
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
50 pF
28 pF
9 pF
tD(on) Turn - On Delay Time
tr Turn - On Rise Time
VDD = 5 V, ID = 0.5 A,
VGS = 4.5 V, RGEN = 50
tD(off) Turn - Off Delay Time
tf Turn - Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
VDS = 5 V, ID = 0.5 A,
VGS = 4.5 V
Qgd Gate-Drain Charge
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
36
8.5 18
17 30
13 25
1.64 2.3
0.38
0.45
ns
ns
ns
ns
nC
nC
nC
IS Maximum Continuous Source Current
0.25 A
VSD Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.25 A (Note 2)
0.8 1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum pad mounting on FR-4 board in still air.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDG6313N Rev. A


Features Datasheet pdf www.DataSheet4U.com April 2002 FDG6313 N Dual N-Channel, Digital FET General D escription These dual N-Channel logic l evel enhancement mode field effect tran sistors are produced using Fairchild's proprietary, high cell density, DMOS te chnology. This very high density proces s is especially tailored to minimize on -state resistance. This device has been designed especially for low voltage ap plications as a replacement for bipolar digital transistors and small signal M OSFETs. Features 25 V, 0.50 A continuo us, 1.5 A peak. RDS(ON) = 0.45 Ω @ VG S= 4.5 V, RDS(ON) =0.60 Ω @ VGS= 2.7 V. Very low level gate drive requiremen ts allowing direct operation in 3 V cir cuits (VGS(th) < 1.5 V). Gate-Source Ze ner for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70 -6 surface mount package. SC70-6 SOT- 23 SuperSOTTM -6 SuperSOTTM -8 SO-8 SOT-223 G2 D1 S2 1 or 4 * 6 or 3 .33 2 or 5 5 or 2 SC70-6 S1 G1 D2 3 or 6 4 or 1 * * The pinouts are symmetrical; pin 1 and 4 are int.
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