CY7C1214H

CY7C1214H www.DataSheet4U.com 1-Mbit (32K x 32) Flow-Through Sync SRAM Features 32K X 32 common I/O 3.3V core power supply (VDD) 2.5V/3.3V I/O power supply (VDDQ) Fast clock-to-output times — 6.5 ns (for 133-MHz version) Provide high-performance 2-1-1-1 access rate User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed write Asynchronous output enable Available in JEDEC-standard lead-free 100-Pin TQFP package “ZZ” Sleep Mode option Functional Description[1] The CY7C1214H is a 32K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1214H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while ...