Document
PH3830L
www.DataSheet4U.com
M3D748
N-channel TrenchMOS™ logic level FET
Rev. 03 — 2 March 2004 Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™ technology.
1.2 Features
s Low thermal resistance s Logic level gate drive s SO8 equivalent area footprint s Low on-state resistance.
1.3 Applications
s DC-to-DC converters s Portable appliances s Switched-mode power supplies s Notebook computers.
1.4 Quick reference data
s VDS ≤ 30 V s Ptot ≤ 62.5 W s ID ≤ 98 A s RDSon ≤ 3.8 mΩ
2. Pinning information
Table 1: Pin 1,2,3 4 mb Pinning - SOT669 (LFPAK), simplified outline and symbol Description source (s)
mb d
Simplified outline
Symbol
gate (g) mounting base; connected to drain (d)
g s
MBB076
1
2
3
4
MBL286
Top view
SOT669 (LFPAK)
Philips Semiconductors
PH3830L
N-channel TrenchMOS™ logic level FET
www.DataSheet4U.com
3. Ordering information
Table 2: Ordering information Package Name PH3830L LFPAK Description Plastic single-ended surface mounted package; 4 leads Version SOT669 Type number
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) gate-source voltage drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 °C peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 70.7 A; tp = 0.1 ms; VDD ≤ 30 V; VGS = 10 V; starting Tj = 25 °C Tmb = 25 °C; VGS = 10 V; Figure 2 and 3 Tmb = 100 °C; VGS = 10 V; Figure 2 Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 150 °C Min −55 −55 Max 30 ±20 98 62 290 62.5 +150 +150 52 150 250 Unit V V A A A W °C °C A A mJ
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
9397 750 12945
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 2 March 2004
2 of 12
Philips Semiconductors
PH3830L
N-channel TrenchMOS™ logic level FET
www.DataSheet4U.com
120 Pder (%) 80
03aa15
120 Ider (%) 80
03aa23
40
40
0 0 50 100 150 200 Tmb (°C)
0 0 50 100 150 200 Tmb (°C)
P tot P der = ---------------------- × 100 % P °
tot ( 25 C )
VGS ≥ 10 V
ID I der = ------------------- × 100 % I °
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of mounting base temperature.
Fig 2. Normalized continuous drain current as a function of mounting base temperature.
103
003aaa377
ID (A)
102
Limit RDSon = VDS / ID tp = 10 µs
10 DC
100 µs 1 ms 10 ms
100 ms 1
10-1 10-1
1
10
VDS (V)
102
Tmb = 25 °C; IDM is single pulse; VGS = 10 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12945
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 2 March 2004
3 of 12
Philips Semiconductors
PH3830L
N-channel TrenchMOS™ logic level FET
www.DataSheet4U.com
5. Thermal characteristics
Table 4: Rth(j-mb) Thermal characteristics Conditions Min Typ Max Unit 2 K/W thermal resistance from junction to mounting base Figure 4 Symbol Parameter
5.1 Transient thermal impedance
10 Zth(j-mb) (K/W)
003aaa378
1
δ = 0.5
0.2 0.1 0.02 0.05
P
single pulse
δ=
tp T
tp T
10-1 10-4 10-3 10-2 10-1 1 tp (s)
t
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 12945
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 03 — 2 March 2004
4 of 12
Philips Semiconductors
PH3830L
N-channel TrenchMOS™ logic level FET
www.DataSheet4U.com
6. Characteristics
Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage VGS(th) gate-source threshold voltage ID = 250 µA; VGS = 0 V ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 150 °C IDSS IGSS RDSon drain-source leakage current gate-source leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 25 °C VGS = ±15 V; VDS = 0 V VGS = 10 V; ID = 25 A; Figure 7 and 8 Tj = 25 °C Tj = 150 °C VGS = 5 V; ID = 25 A; Figure 7 Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 reverse recovery time IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V VDD = 15 V; ID = 20 A; VGS = 4.5 V; RG = 4.7 Ω VGS = 0 V; VDS = 10 V; f = 1 MHz; Figure 11 ID = 20 A; VDD = 10 V; VGS = 5 V; Figure 13 33 11 11 nC nC nC pF pF pF ns ns ns ns V ns 3.2 5.4 4 3.8 6.5 4.9 mΩ mΩ mΩ 1 0.65 1.5 0.06 20 2 1 100 V V µA nA 30 V Conditions Min T.