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92CD54IF Dataheets PDF



Part Number 92CD54IF
Manufacturers Toshiba Semiconductor
Logo Toshiba Semiconductor
Description TMP92CD54IF
Datasheet 92CD54IF Datasheet92CD54IF Datasheet (PDF)

www.datasheet4u.com TMP92CD54I CMOS 32-bit Micro-controller TMP92CD54IF 1. Outline and Device Characteristics TMP92CD54I is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CD54I is a micro-controller which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92CD54I is housed in a 100-pin mini flat package. Device characteristics are as follows: (1) CPU : 32-bit CPU(900/H1 CPU) Compatible with TLCS-900,900/L,900/L.

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www.datasheet4u.com TMP92CD54I CMOS 32-bit Micro-controller TMP92CD54IF 1. Outline and Device Characteristics TMP92CD54I is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP92CD54I is a micro-controller which has a high-performance CPU (900/H1 CPU) and various built-in I/Os. TMP92CD54I is housed in a 100-pin mini flat package. Device characteristics are as follows: (1) CPU : 32-bit CPU(900/H1 CPU) Compatible with TLCS-900,900/L,900/L1,900/H,900/H2’s instruction code 16Mbytes of linear address space General-purpose register and register banks Micro DMA : 8channels (250ns / 4bytes at fc = 20MHz, best case) Minimum instruction execution time : 50ns(at 20MHz) Internal data bus : 32-bit Internal memory Internal RAM : 32K-byte Internal ROM : 512K-byte Mask ROM (2) 92CD54I-1 2006-01-27 www.datasheet4u.com TMP92CD54I (3) (4) (5) External memory expansion 16M-byte linear address space (memory mapped I/O) External data bus : 8bit(for external I/O expansion) * Can’t use upper address bus when built-in I/Os are selected Memory controller (MEMC) Chip select output : 1 channel 8-bit timer : 8 channels 8-bit interval timer mode (8 channels) 16-bit interval timer mode (4 channels) 8-bit programmable pulse generation (PPG) output mode (4 channels) 8-bit pulse width modulation (PWM) output mode (4 channels) 16-bit timer : 2 channels 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) output mode Frequency measurement mode Pulse width measurement mode Time differential measurement mode Serial interface (SIO) : 2 channels I/O interface mode Universal asynchronous receiver transmitter (UART) mode Serial expansion interface (SEI) : 1 channel Baud rate 4/2/0.5Mbps at fc=20MHz. (6) (7) (8) (9) Serial bus interface (SBI) : 3 channels Clocked-synchronous 8-bit serial interface mode I2C bus mode (10) CAN controller : 1channel Supports CAN version 2.0B. 16 mailboxes (11) 10-bit A/D converter (ADC) : 12 channels A/D conversion time 8µsec @fc=20MHz. Total tolerance +/- 3LSB (excluding quantization error) Scan mode for all 12channels (12) Watch dog timer (WDT) (13) Timer for real-time clock (RTC) Can operate with only low frequency oscillator. (14) Interrupt controller (INTC) : 60 interrupt sources 9 interrupts from CPU 42 internal interrupt vectors 9 external interrupt vectors (15) I/O Port : 68pins (16) Standby mode Four modes : IDLE3,IDLE2,IDLE1 and STOP STOP mode can be released by 9 external inputs. (17) Internal voltage detection flag (RAMSTB) 92CD54I-2 2006-01-27 www.datasheet4u.com TMP92CD54I (18) Power supply voltage VCC5 = 4.5V to 5.25V VCC3 = 3.3V (VCC3 Connect to REGOUT; built-in voltage regulator.) (19) (20) Operating temperature : -40 to 85 degree C Package : P-LQFP100-1414-0.50F 92CD54I-3 2006-01-27 www.datasheet4u.com TMP92CD54I PG0toPG7 (AN0toAN7) PL0toPL3 (AN8toAN11) ADVCC ADVSS VREFH VREFL (TXD0)PF0 (RXD0)PF1 (SCLK0/ CTS0 )PF2 (TXD1)PF3 (RXD1)PF4 (SCLK1/ CTS1 )PF5 (TX)PF6 (RX)PF7 (TI0/INT1)PC0 (TO1)PC1 10-BIT 12CH A/D CONVERTER XWA XBC XDE SERIAL I/O Channel 0 SERIAL I/O Channel 1 CAN CONTROLLER W B D H IX IY IZ SP 32 bits SR P C A C E L Regulator REGEN REGOUT X1 X2 CLK XT1 XT2 RESET XHL XIX XIY XIZ XSP OSC RTC F INTERRUPT CONTROLLER AM0 AM1 TEST0 TEST1 NMI INT0 P00toP07 (D0toD7) P40toP47 (A0toA7) P70( RD ) P71( WR ) P73( CS ) P74 P75( WAIT ) PN0(SCK0) PN1(SO0/SDA0) PN2(SI0/SCL0) PN3(SCK1/A12) PN4(SO1/SDA1/A13) PN5(SI1/SCL1/A14) PM4(SCK2) PN6(SO2/SDA2/A15) P72(SI2/SCL2) 8BIT TIMER (TIMER0) 8BIT TIMER (TIMER1) 8BIT TIMER (TIMER2) WATCH-DOG TIMER REAL TIME CLOCK (RTC) PORT0 PORT4 32KB RAM PORT7 (TO3/INT2)PC2 (TI4/INT3)PC3 8BIT TIMER (TIMER3) 8BIT TIMER (TIMER4) 8BIT TIMER (TIMER5) 8BIT TIMER (TIMER6) 8BIT TIMER (TIMER7) 16BIT TIMER (TIMER8) 16BIT TIMER (TIMERA) Figure 1 TMP92CD54I block diagram SERIAL EXP.I/F 512KB Mask ROM SERIAL BUS I/F Channel 0 SERIAL BUS I/F Channel 1 SERIAL BUS I/F Channel 2 (TO5)PC4 (TO7/INT4)PC5 (TI8/WUINT0/INT5/A16)PD0 (TI9/WUINT1/INT6/A17)PD1 (TO8/WUINT2/A18)PD2 (TO9/WUINT3/A19)PD3 (TIA/WUINT4/INT7/A20)PD4 (TIB/WUINT5/A21)PD5 (TOA/WUINT6/A22)PD6 (TOB/WUINT7/A23)PD7 PM0( SS /A8) PM1(MOSI/A9) PM2(MISO/A10) PM3(SECLK/A11) 92CD54I-4 2006-01-27 CONNECT 900/H1 CPU DVSS[6] DVCC5[5] DVCC3[3] www.datasheet4u.com TMP92CD54I 2. Pin Assignment and Functions 2.1 Pin Assignment 095 090 085 080 ADVSS ADVCC VREFL VREFH RX/PF7 TX/PF6 CTS1/SCLK1/PF5 RXD1/PF4 TXD1/PF3 CTS0/SCLK0/PF2 RXD0/PF1 TXD0/PF0 DVSS PM4/SCK2 DVCC5 A8/SS/PM0 A9/MOSI/PM1 A10/MISO/PM2 A11/SECLK/PM3 D0/P00 D1/P01 D2/P02 D3/P03 D4/P04 D5/P05 01 076 100 PL3/AN11 PL2/AN10 PL1/AN9 PL0/AN8 PG7/AN7 PG6/AN6 PG5/AN5 PG4/AN4 PG3/AN3 PG2/AN2 PG1/AN1 PG0/AN0 DVSS P75/WAIT DVCC3 P74 P73/CS P72/SI2/SCL2 P71/WR P70/RD AM0 RESET AM1 CLK TEST0 75 05 70 10 TMP92CD54IF (P-LQFP100-1414-0.50F) 65 14 x 14 x 1.4 15 TOP VIEW 60 20 55 26 30 35 40 45 D6/P06 D7/P07 A0/P40 A1/P41 A2/P42 A3.


EER28 92CD54IF 2SK2644-01


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