MSPS ADC. CDK1300 Datasheet

CDK1300 ADC. Datasheet pdf. Equivalent

Part CDK1300
Description 250 MSPS ADC
Feature Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e CDK1300 8-bit, 250 MSPS ADC with Demux.
Manufacture Cadeka
Datasheet
Download CDK1300 Datasheet



CDK1300
Data Sheet
Amplify the Human Experience
CDK1300
8-bit, 250 MSPS ADC with Demuxed Outputs
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features
n TTL/CMOS/PECL input logic compatible
n High conversion rate: 250 MSPS
n Single +5V power supply
n Very low power dissipation: 310mW
n 220MHz full power bandwidth
n Power-down mode
n +3.0V/+5.0V (LVCMOS) digital output
logic compatibility
n Single/demuxed output ports selectable
Applications
n RGB video processing
n Digital communications
n High-speed instrumentation
n Digital Sampling Oscilloscopes (DSO)
n Projection display systems
General Description
The CDK1300 is a high-speed, 8-bit analog-to-digital converter implemented
in an advanced BiCMOS process. An advanced folding and interpolating
architecture provides both a high conversion rate and very low power
dissipation of only 310mW. The analog inputs can be operated in
either single-ended or differential input mode. A 2.5V common mode
reference is provided on chip for the single-ended input mode to minimize
external components.
The CDK1300 digital outputs are demuxed (double-wide) with both dual-
channel and single-channel selectable output modes. Demuxed mode
supports either parallel aligned or interleaved data output. The output logic
is both +3.0V and +5.0V compatible. The CDK1300 is available in a 44-lead
TQFP surface mount package over the industrial temperature range of -40°C
to +85°C.
Block Diagram
Ordering Information
Part Number
CDK1300ITQ44
CDK1300ITQ44_Q
Package
TQFP-44
TQFP-44
Moisture sensitivity level for all parts is MSL-1.
Pb-Free
Yes
No
RoHS Compliant
Yes
No
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
Packaging Method
Rail
Rail
©2008 CADEKA Microcircuits LLC
www.cadeka.com



CDK1300
Data Sheet
Pin Configuration
TQFP-44
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CDK1300
Pin Assignments
Pin No.
40
39
16-9
19-26
28
27
4
3
Pin Name
VIN+
VIN-
DA0–DA7
DB0–DB7
DCLKOUT
DCLKOUT
CLK
CLK
5 RESET
6 RESET
32, 31
DMODE1,2
2
37
35, 36,
42, 43
7, 17, 30
1, 33, 34,
38, 41, 44
8, 18, 29
PD
VCM
AVCC
OVDD
AGND
DGND
Description
Non-inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally
Inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally
Data output bank A; 3V/5V LVCMOS compatible
Data output bank B; 3V/5V LVCMOS compatible
Non-inverted data output clock; 3V/5V LVCMOS compatible
Inverted data output clock; 3V/5V LVCMOS compatible
Non-inverted clock input pin; 100k pulldown to AGND, internally
Inverted clock input pin; 17.5k pullup to Vcc and 7.5k pulldown to AGND, internally
RESET synchronizes the data sampling and data output bank relationship when in dual channel
mode (DMODE1 = 0); 100k pulldown to AGND, internally
Inverted RESET input pin; 17.5k pullup to Vcc and 7.5 pulldown to AGND, internally
Internally: 100k pulldown to AGND on DMODE1 50k pullup to Vcc on DMODE2
Data output mode pins: DMODE1 = 0, DMODE2 = 0: parallel dual channel output
DMODE1 = 0, DMODE2 = 1: interleaved dual channel output
DMODE1 = 1, DMODE2 = x: single channel data output on bank a (125 MSPS max)
Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down
mode; 100k pulldown to AGND, internally
2.5V common mode voltage reference output
+5V analog supply
+3V/+5V digital output supply
Analog ground
Digital ground
©2008 CADEKA Microcircuits LLC
www.cadeka.com 2





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