RAM. IC42S32200L Datasheet
512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
Integrated Circuit Systems
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Obselete partial refresh function
Obselete 5ns speed grade
Change ICC3P from 3mA to 5mA
Revise p.20,p.22 data and p.28 typo
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
512K Words x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
ww· wC.doantacsuhrereetn4tu.acuomto precharge
· Clock rate:166/143/125 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (512K x 32bit x 4bank)
· Programmable Mode
-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· Single +3.3V ±0.3V power supply
· Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin
Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm
· Pb-free package is available.
The ICSI IC42S32200 and IC42S32200L is a high-speed
CMOS configured as a quad 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).
Each of the 512K x 32 bit banks is organized as 2048 rows
by 256 columns by 32 bits.Read and write accesses start
at a selected locations in a programmed sequence.
Accesses begin with the registration of a BankActive
command which is then followed by a Read or Write
The ICSI IC42S32200 and IC42S32200L provides for
programmable Read or Write burst lengths of 1,2,4,8,or
full page, with a burst termination operation. An auto
precharge function may be enable to provide a self-timed
row precharge that is initiated at the end of the burst
sequence.The refresh functions,either Auto or Self
Refresh are easy to use.
By having a programmable mode register,the system
can choose the most suitable modes to maximize its
These devices are well suited for applications requiring
high memory bandwidth.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
|Features||Datasheet pdf IC42S32200 IC42S32200L Document Title 5 12K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History www.datasheet4u.com Re vision No History Initial Draft Obsel ete partial refresh function Obselete 5 ns speed grade Change ICC3P from 3mA to 5mA Revise typo Revise p.20,p.22 data and p.28 typo Draft Date September 26, 2002 September 05,2003 April 27,2004 Fe bruary 04,2005 Remark 0A 0B 0C 0D Th e attached datasheets are provided by I CSI. Integrated Circuit Solution Inc re serve the right to change the specifica tions and products. ICSI will answer to your questions about device. If you ha ve any questions, please contact the IC SI offices. Integrated Circuit Solutio n Inc. DR036-0D 02/04/2005 1 IC42S322 00 IC42S32200L 512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC R AM FEATURES · Concurrent auto www.data sheet4u.com precharge · Clock rate:166 /143/125 MHz · Fully synchronous opera tion · Internal pipelined architecture · Four internal banks (512K x 32bit x 4bank) · Programmable Mode -.|
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