DYNAMIC RAM. IC42S32200L Datasheet

IC42S32200L RAM. Datasheet pdf. Equivalent

IC42S32200L Datasheet
Recommendation IC42S32200L Datasheet
Part IC42S32200L
Description 512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
Feature IC42S32200L; IC42S32200 IC42S32200L Document Title 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History www..
Manufacture Integrated Circuit Systems
Datasheet
Download IC42S32200L Datasheet




Integrated Circuit Systems IC42S32200L
IC42S32200
IC42S32200L
Document Title
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Revision History
www.datasheet4Ru.ecvomision No
0A
0B
0C
0D
History
Initial Draft
Obselete partial refresh function
Obselete 5ns speed grade
Change ICC3P from 3mA to 5mA
Revise typo
Revise p.20,p.22 data and p.28 typo
Draft Date
September 26,2002
September 05,2003
Remark
April 27,2004
February 04,2005
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
1



Integrated Circuit Systems IC42S32200L
IC42S32200
IC42S32200L
512K Words x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
ww· wC.doantacsuhrereetn4tu.acuomto precharge
· Clock rate:166/143/125 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (512K x 32bit x 4bank)
· Programmable Mode
-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
-Burst-Read-Single-Write
· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· Single +3.3V ±0.3V power supply
· Interface:LVTTL
· Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin
Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm
· Pb-free package is available.
DESCRIPTION
The ICSI IC42S32200 and IC42S32200L is a high-speed
CMOS configured as a quad 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).
Each of the 512K x 32 bit banks is organized as 2048 rows
by 256 columns by 32 bits.Read and write accesses start
at a selected locations in a programmed sequence.
Accesses begin with the registration of a BankActive
command which is then followed by a Read or Write
command
The ICSI IC42S32200 and IC42S32200L provides for
programmable Read or Write burst lengths of 1,2,4,8,or
full page, with a burst termination operation. An auto
precharge function may be enable to provide a self-timed
row precharge that is initiated at the end of the burst
sequence.The refresh functions,either Auto or Self
Refresh are easy to use.
By having a programmable mode register,the system
can choose the most suitable modes to maximize its
performance.
These devices are well suited for applications requiring
high memory bandwidth.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
DR036-0D 02/04/2005



Integrated Circuit Systems IC42S32200L
IC42S32200
IC42S32200L
FUNCTIONAL BLOCK DIAGRAM
www.datasheet4u.com
CLK
CKE
CS#
RAS#
CAS#
WE#
CLOCK
BUFFER
COMMAND
DECODER
A10/AP
COLUMN
COUNTER
CONTROL
SIGNAL
G E N E R AT O R
MODE
REGISTER
A0
A9
BS0
BS1
ADDRESS
BUFFER
REFRESH
COUNTER
DQ0
D Q 31
DQ
BUFFER
DQM0~3
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
Column Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #0)
Sense Amplifier
Sense Amplifier
2048 X 256 X 32
CELL ARRAY
(BANK #1)
Column Decoder
Column Decoder
2048 X 256 X 32
CELL ARRAY
(BANK #2)
Sense Amplifier
Sense Amplifier
2048 X 256 X 32
CELL ARRAY
(BANK #3)
Column Decoder
3





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