(PDF) IC42S32202 Datasheet PDF | Integrated Circuit Solution





IC42S32202 Datasheet PDF

Part Number IC42S32202
Description 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Manufacture Integrated Circuit Solution
Total Page 30 Pages
PDF Download Download IC42S32202 Datasheet PDF

Features: Datasheet pdf IC42S32202/L Document Title 512K x 32 B it x 4 Banks (64-MBIT) SDRAM Revision H istory www.datasheet4u.com Revision No History Initial Draft Draft Date Aug ust 17,2004 Remark 0A The attached d atasheets are provided by ICSI. Integra ted Circuit Solution Inc reserve the ri ght to change the specifications and pr oducts. ICSI will answer to your questi ons about device. If you have any quest ions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR042 -0C 08/17/2004 1 IC42S32202/L 512K W ords x 32 Bits x 4 Banks (64-MBIT) SYNC HRONOUS DYNAMIC RAM FEATURES · Concurr ent auto www.datasheet4u.com precharge · Clock rate:166/143/125 MHz · Fully synchronous operation · Internal pipel ined architecture · Four internal bank s (512K x 32bit x 4bank) · Programmabl e Mode -CAS#Latency:2 or 3 -Burst Lengt h:1,2,4,8,or full page -Burst Type:inte rleaved or linear burst -Burst-Read-Sin gle-Write · Burst stop function · Ind ividual byte controlled by DQM0-3 · Auto Refresh and Self Refresh · 409.

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IC42S32202 datasheet
IC42S32202/L
Document Title
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Revision History
www.datasheet4Ru.ecvomision No
0A
History
Initial Draft
Draft Date
August 17,2004
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004
1

IC42S32202 datasheet
IC42S32202/L
512K Words x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
ww· wC.doantacsuhrereetn4tu.acuomto precharge
· Clock rate:166/143/125 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (512K x 32bit x 4bank)
· Programmable Mode
-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
-Burst-Read-Single-Write
· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· Single +3.3V ±0.3V power supply
· Interface:LVTTL
· Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin
Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm
· Pb-free package is available.
DESCRIPTION
The ICSI IC42S32202 and IC42S32202L is a high-speed
CMOS configured as a quad 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).
Each of the 512K x 32 bit banks is organized as 2048 rows
by 256 columns by 32 bits.Read and write accesses start
at a selected locations in a programmed sequence.
Accesses begin with the registration of a BankActive
command which is then followed by a Read or Write
command
The ICSI IC42S32202 and IC42S32202L provides for
programmable Read or Write burst lengths of 1,2,4,8,or
full page, with a burst termination operation. An auto
precharge function may be enable to provide a self-timed
row precharge that is initiated at the end of the burst
sequence.The refresh functions,either Auto or Self
Refresh are easy to use.
By having a programmable mode register,the system
can choose the most suitable modes to maximize its
performance.
These devices are well suited for applications requiring
high memory bandwidth.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2 Integrated Circuit Solution Inc.
DR042-0C 08/17/2004





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