512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
IC42S32202/L
Document Title
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Revision History
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No
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Description
IC42S32202/L
Document Title
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Revision History
www.datasheet4u.com Revision
No
History
Initial Draft
Draft Date
August 17,2004
Remark
0A
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004
1
IC42S32202/L
512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
FEATURES
· Concurrent auto www.datasheet4u.com precharge · Clock rate:166/143/125 MHz · Fully synchronous operation · Internal pipelined architecture · Four internal banks (512K x 32bit x 4bank) · Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:interleaved or linear burst -Burst-Read-Single-Write · Burst stop function · Individual byte controlled by DQM0-3 · Auto Refresh and Self Refresh · 4096 refresh cycles/64ms · Single +3.3V ±0.3V power supply · Interface:LVTTL · Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm · Pb-free package is available.
DESCRIPTION
The ICSI IC42S32202 and IC42S32202L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits.Re...
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