E1/T1 Mapper. CP1181 Datasheet

CP1181 Mapper. Datasheet pdf. Equivalent

Part CP1181
Description 21 ch E1/T1 Mapper
Feature CP1181 Product Brief OPTRANS Series CP1181_PB_Rev1.0 March, 2005 21 Channel E1/T1 Mapper www.datash.
Manufacture CHIP
Total Page 3 Pages
Datasheet
Download CP1181 Datasheet



CP1181
21 Channel E1/T1 Mapper
Product Brief
CP1181
OPTRANS Series
CP1181_PB_Rev1.0 March, 2005
www.daOtasVheEet4Ru.cVomIEW
The CP1181 is one of the OPTRANS series chips designed by Chiphomer
Technology Limited. It is designed for add/drop multiplexer, terminal
multiplexer, dual and single unidirectional ring applications. 21 E1/T1
signals are mapped to and from asynchronous TU12. The CP1181 interfaces
to a byte-wide 19.44 MHz Telecom Bus.
FEATURES
Asynchronously mapping/de-mapping 21 E1 or T1 traffics into/from
STM-1. T1 traffic mapping path is T1 VC11 TU12.
Configurable receive and transmit TU12 time-slots via microprocessor
Detects loss of input clock on Telecom Bus
TEBGA256
-40 ~ 85
Interprets TU12 pointer according to G.783 (2000/10) and G.707 (2000/10)
Detects LOM, TU-LOP and TU-AIS alarms
Detects Remote Defect Indication (RDI), Remote Error Indication (REI), RFI alarm and Path Label Mismatch
(PLM) alarm
Provides 12-bit performance counters for BIP-2 errors and 11-bit performance counters for tributary REI errors
Detects degraded signals(DEG) and Excessive Error defects (EXC) based on received BIP-2 errors.
Extracts the 16-byte J2 sequence into microprocessor accessible registers, and checks the J2 sequence to detect
TIM alarm
Detects the K4 (bit5-bit7) and V5 bit8 for Enhanced Defect Indicator (E-RDI)
Captures filtered K4 byte into microprocessor accessible registers
Extracts V5 and K4 bytes into microprocessor accessible registers
Extracts N2 byte and O bits into microprocessor accessible registers
RTCLKA
RTPLA
RTMFA
RTJ0J1V1A
RTDA[7:0]
RTPARA
RTINDA
RTCLKB
RTPLB
RTMFB
RTJ0J1V1B
RTDB[7:0]
RTPARB
RTINDB
TTCLKA
TTPLA
TTMFA
TTJ0J1V1A
TTDA[7:0]
TTPARA
TTINDA
TTCLKB
TTPLB
TTJ0J1V1B
TTMFB
TTDB[7:0]
TTPARB
TTINDB
Pointer
Interpreter A
POH
Terminate A
Pointer
Interpreter B
POH
Terminate B
DPLL
Mux Desync
Switching
Control
PRBS
Analyzer
Mux
Mux
Pointer
Generator A
POH Build A
Pointer
Generator B
POH Build B
Sync
Mux
Mux
PRBS
Generator
Microprocessor Interface
E1_TDATA[0..20]/
T1_DATA[0..20]
E1_TCLK[0..20]/
T1_TCLK[0..20]
E1_RDATA[0..20]/
T1_RDATA[0..20]
E1_RCLK[0..20]/
T1_RCLK[0..20]
Copyright ©2005 Chiphomer Technology Limited
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CP1181
21 Channel E1/T1 Mapper
Product Brief
CP1181
OPTRANS Series
CP1181_PB_Rev1.0 March, 2005
Supports1+1 Path-protection
www.datasheeInt4tue.gcroamted bit-leaking circuit and DPLL
The output jitter of E1/T1 data (either mapping jitter or combined jitter) is compliant with G.783 (2000/10)
E1/T1 Port #0 to Port #7 can be configured to work in re-timing mode
Supports the code-rate adjustment
Optionally inserts VC-AIS and TU-AIS into upstream data
Generates the TU12 pointer (V1, V2) per ITU G.783
The TU12 pointer value is fixed on 105
Calculates the BIP-2 and inserts into outgoing data stream, optionally inserts single or continued BIP-2 errors
Inserts RDI/REI from either internal generation or microprocessor
Inserts 16-byte programmable J2 sequence
Inserts E-RDI from either internal generation or microprocessor
Inserts programmable N2 byte and O bits
Controlled High-Z output on transmit Telecom Bus
Provides three bus timing modes for transmit Telecom Bus
Build-in PRBS test function can be configured to any one of all 21 E1/T1 ports
Provides 16-bit Intel/Motorola microprocessor interface
3.3V supply with 5V tolerant I/O
IEEE 1149.1 JTAG boundary scan
Maximum power less than 1.0 Watt
Operating industrial temperature range: -40~ 85
PBGA256 package
APPLICATIONS
SDH Add/Drop Multiplexers
SDH Terminal Multiplexers
Multi-service Transport Platform (MSTP)
TYPICAL APPLICATION
Add Bus A
Add Bus B
Drop Bus A
Drop Bus B
21ch E1/T1 Mapper
CP1181
8ch8CLc8CEHIhcUH15hL/05TLI00U18I0U8
CP5009
21 E1/T1
19.44MHz Telecom Bus
Copyright ©2005 Chiphomer Technology Limited
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