MAX3625

19-1010; Rev 0; 10/07 Low-Jitter, Precision Clock Generator with Three Outputs www.datasheet4u.com General Description ♦ CMOS Input: Up to 320MHz Features ♦ Crystal Oscillator Interface: 24.8MHz to 27MHz ♦ Output Frequencies Ethernet: 125MHz, 156.25MHz, 312.5MHz 10G Fibre Channel: 159.375MHz, 318.75MHz ♦ Low Jitter 0.14psRMS (1.875MHz to 20MHz) 0.38psRMS (12kHz to 20MHz) ♦ Excellent Power-Supply Noise Rejection ♦ No External Loop Filter Capacitor Required MAX3625 The MAX3625 is a low-jitter precision clock generator optimized for networking applications. The device integrates a crystal oscillator and a phase-locked loop (PLL) clock multiplier to generate high-frequency clock outputs for Ethernet, 10G Fibre Channel, and other networking applications. Maxim’s proprietary PLL design features ultra-low jitter and excellent power-supply noise rejection, minimizing design risk for network equipment. The MAX3625 has three LVPECL outputs. Selectable output dividers and a selectable feedback divider allow a range of output frequencies. Applications Ethernet Networking Equipment Fibre Channel Storage Area Network PART MAX3625CUG+ Ordering Information TEMP RANGE PIN-PACKAGE 0°C to +70°C 24 TSSOP PKG CODE U24-1 Pin Configuration and Typical Application Circuit appear at end of data sheet. +Denotes a lead-free package. Block Diagram IN_SEL MR BYPASS SELA[1:0] SELA[1:0] SELB[1:0] FB_SEL BYPASS QA_OE RESET LOGIC/POR RESET DIVIDER NA LVPECL BUFFER QA QA RESET LVCMOS REF_IN 27pF ...