AS7C1024B

March 2004 ® AS7C1024B 5V 128K X 8 CMOS SRAM Features www.datasheet4u.com Industrial and commercial temperatures Organization: 131,072 words x 8 bits High speed - 10/12/15/20 ns address access time - 5/6/7/8 ns output enable access time Low power consumption: ACTIVE - 605 mW / max @ 10 ns ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA - 300 mil SOJ 400 mil SOJ 8 × 20mm TSOP 1 8 x 13.4mm sTSOP 1 Low power consumption: STANDBY - 55 mW / max CMOS 6T 0.18u CMOS technology Easy memory expansion with CE1, CE2, OE inputs TTL/LVTTL-compatible, three-state I/O 32-pin JEDEC standard packages Pin arrangement 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 Logic block diagram VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7 Row decoder 512 x 256 x 8 Array (1,048,576) Sense amp 32-pin (8 x 20mm) TSOP I 32-pin (8 x 13.4mm) sTSOP1 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 I/O0 WE OE CE1 CE2 Column decoder Control circuit Selection guide -10 Maximum address access time Maximum output enable access time Maximum Operating Current Maximum CMOS standby Current 10 5 110 10 -12 A9...