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PHB160NQ08T Dataheets PDF



Part Number PHB160NQ08T
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description N-channel TrenchMOS standard level FET
Datasheet PHB160NQ08T DatasheetPHB160NQ08T Datasheet (PDF)

PHP/PHB160NQ08T N-channel TrenchMOS™ standard level FET Rev. 01 — 28 January 2004 www.datasheet4u.com Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™ technology. 1.2 Features s Standard level threshold s Very low on-state resistance. 1.3 Applications s Motors, lamps, solenoids s DC-to-DC converters s Uninterruptable power supplies s General industrial applications. 1.4 Quick reference data s VDS ≤ 7.

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PHP/PHB160NQ08T N-channel TrenchMOS™ standard level FET Rev. 01 — 28 January 2004 www.datasheet4u.com Product data 1. Product profile 1.1 Description N-channel enhancement mode field-effect power transistor in a plastic package using TrenchMOS™ technology. 1.2 Features s Standard level threshold s Very low on-state resistance. 1.3 Applications s Motors, lamps, solenoids s DC-to-DC converters s Uninterruptable power supplies s General industrial applications. 1.4 Quick reference data s VDS ≤ 75 V s Ptot ≤ 300 W s ID ≤ 75 A s RDSon ≤ 5.6 mΩ. 2. Pinning information Table 1: 1 2 3 mb Pinning - SOT78 (TO-220AB) and SOT404 (D2-PAK), simplified outline and symbol Simplified outline [1] Pin Description gate (g) drain (d) source (s) mounting base; connected to drain (d) Symbol mb d mb g s MBB076 2 1 MBK106 3 MBK116 1 2 3 SOT78 (TO-220AB) [1] It is not possible to make connection to pin 2 of the SOT404 package. SOT404 (D2-PAK) Philips Semiconductors PHP/PHB160NQ08T N-channel TrenchMOS™ standard level FET 3. Ordering information www.datasheet4u.com Table 2: Ordering information Package Name Description Version TO-220AB D2-PAK Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 leads SOT78 Plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404 Type number PHP160NQ08T PHB160NQ08T 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 °C peak source (diode forward) current Tmb = 25 °C; pulsed; tp ≤ 10 µs unclamped inductive load; ID = 75 A; tp = 0.15 ms; VDD ≤ 75 V; RGS = 50 Ω; VGS = 10 V; starting Tj = 25 °C Tmb = 25 °C; VGS = 10 V; Figure 2 and 3 Tmb = 100 °C; VGS = 10 V; Figure 2 Tmb = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tmb = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 175 °C 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ Min −55 −55 Max 75 75 ±20 75 75 240 300 +175 +175 75 240 560 Unit V V V A A A W °C °C A A mJ Source-drain diode Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy 9397 750 12719 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 28 January 2004 2 of 13 Philips Semiconductors PHP/PHB160NQ08T N-channel TrenchMOS™ standard level FET www.datasheet4u.com 120 Pder (%) 80 03aa16 120 Ider (%) 80 03ap65 40 40 0 0 50 100 150 200 Tmb (°C) 0 0 50 100 150 200 Tmb (°C) P tot P der = ---------------------- × 100 % P ° tot ( 25 C ) ID I der = ------------------- × 100 % I ° D ( 25 C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature. Fig 2. Normalized continuous drain current as a function of mounting base temperature. 103 ID (A) Limit RDSon = VDS / ID 03ap67 tp = 10 µ s 102 1 ms 10 ms DC 10 100 ms 1s 1 1 10 102 VDS (V) 103 Tmb = 25 °C; IDM is single pulse; VGS = 10 V. Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage. 9397 750 12719 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 28 January 2004 3 of 13 Philips Semiconductors PHP/PHB160NQ08T N-channel TrenchMOS™ standard level FET 5. Thermal characteristics www.datasheet4u.com Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ 60 50 Max 0.5 Unit K/W K/W K/W thermal resistance from junction to mounting base Figure 4 thermal resistance from junction to ambient SOT78 SOT404 vertical in still air mounted on a printed-circuit board; minimum footprint. Symbol Parameter 5.1 Transient thermal impedance 1 Zth(j-mb) (K/W) δ = 0.5 03ap66 0.2 10-1 0.1 0.05 0.02 single pulse P δ= tp T tp T 10-2 10-4 10-3 10-2 10-1 t tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration. 9397 750 12719 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 01 — 28 January 2004 4 of 13 Philips Semiconductors PHP/PHB160NQ08T N-channel TrenchMOS™ standard level FET 6. Characteristics www.datasheet4u.com Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 °C Tj = 175 °C Tj = −55 °C IDSS drain-source leakage current VDS = 75 V; VGS = 0 V Tj = 25 °C Tj = 175 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±20 V; VDS = 0 V VGS = 10 V; ID = 25 A; Figure 7 and 8 Tj = 25 °C Tj = 175 °C Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain (Miller) charge input capacitan.


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